NET CPU Cycles per instruction

[PBT]

I am debugging performance on NRF5340 NET CPU using RTIMER to measure execution time and DWT Cycle counters to measure cycles.
Both along pretty well, but when I compare executed cycles with the  corresponding assembler there is a big mismatch:
When I count number of instructions in a loop multiplied with number of iterations, the number of cycles is more than 2 times higher.

This cannot be right?

Best
Peter

[PBT]

It seems like the NVMC ICACHE was not enabled in this codebase and that with the flash wait state should explain my findings.

Best

Peter

[PBT]

Enabling the NVMC I-Cache using NRFX indeed reduced cycle count by factor 2+.

Best

Peter