Does fds_gc () affect nrf_drv_timer?

[MaSo]

Thank you for viewing my question.

I am manually doing PWM control of LEDs in nrf_drv_timer.
For example, timer is a period every 100 ms, of which 2-ms is HIGH and 80 ms is LOW.
So far, so good.
However, if I do fds_gc () within the Timer period, the LED will become unstable for a short time, and then there will be no problem.
(1) Does fds_gc affect timer?
(2) Is there a way to control PWM during fds_gc?

[tesc]

Hi,

During garbage collection there will be a number of flash page erases. Each flash page erase on the nRF52832 takes from 2.05 to 89.7 ms, according to the Non-volatile memory controller (NVMC) electrical specification. During this period the CPU is halted. If your PWM implementation relies on CPU, i.e. is not using hardware PWM peripherals but rather an interrupt based approach with a timer calling interrupt routines, flash erases are expected to lead to delayed state changes on the PWM, yes.

If you need concurrent flash operation and PWM, that can be done through use of the PWM peripheral or through using Programmable peripheral interconnect (PPI) for connecting timer events directly to GPIO changes in hardware. Depending on the use case, you might get some benefit from EasyDMA as well (giving peripherals direct access to RAM, meaning no CPU needed for feeding certain types of data to or from hardware registers.)

Regards,
Terje

[MaSo]

Thank you very much. I solved it.

[tesc]

Hi,

I am happy to hear that you solved it. If you consider my answer to be correct, then please verify it. That way it will be easier for others to find it in the future.

Regards,
Terje