I want to generate a 3MHz clock using PWM with 50% duty cycle.

[Jithin A]

Hi, I am new to the NRF environment.

I am working on a nRF5340 project where I need to generate a 3MHz clock for data communication with 50% duty cycle, I see only even frequencies are available for PWM configuration.

Below is my code snippet:

static nrf_pwm_values_common_t sequenceValues[] = {1};

nrf_pwm_sequence_t sequence ={
	.values.p_common = sequenceValues,
	.length              = NRF_PWM_VALUES_LENGTH(sequenceValues),
	.repeats             = 0,
	.end_delay           = 0
};
	
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT] = {CLOCK_PIN, NRF_PWM_PIN_NOT_CONNECTED, NRF_PWM_PIN_NOT_CONNECTED, NRF_PWM_PIN_NOT_CONNECTED};

void pwm_init (void)
{
    nrf_pwm_enable(NRF_PWM1);
    
    nrf_pwm_pins_set(NRF_PWM1, out_pins);
    nrf_pwm_decoder_set(NRF_PWM1, PWM_DECODER_LOAD_Common, NRF_PWM_STEP_AUTO);
    nrf_pwm_configure(NRF_PWM1, NRF_PWM_CLK_8MHz, NRF_PWM_MODE_UP , 2);
    nrf_pwm_sequence_set(NRF_PWM1, 0, &sequence);
    nrf_pwm_int_set(NRF_PWM1, 0);
    nrf_pwm_event_clear(NRF_PWM1, NRF_PWM_EVENT_LOOPSDONE);
    nrf_pwm_event_clear(NRF_PWM1, NRF_PWM_EVENT_SEQEND0);
    nrf_pwm_event_clear(NRF_PWM1, NRF_PWM_EVENT_SEQEND1);
    nrf_pwm_event_clear(NRF_PWM1, NRF_PWM_EVENT_STOPPED);
}

The above code is able to generate 4MHz clock with 66% duty cycle.

NOTE: This is integrated inside TF-M application, so we have used NRF libraries.

Please guide me to generate 3MHz clock with 50% duty cycle.

[Sigurd]

Hi,

Please guide me to generate 3MHz clock with 50% duty cycle.

It's not possible to get exactly 3MHz with 50% duty cycle. Closest possible is 3.2MHz with either ~63 or ~43 % duty cycle.

(With an PWM base clock at 16MHz, if you set "top-value", which is an integer to 5, you get 16/5 = 3.2MHz)