Zephyr - Changing SPI Frequency on NRF52840DK

[Jeff Maigemu]

I am integrating the Zephyr SPI Bitbang example located here zephyr/samples/drivers/spi_bitbang at main · zephyrproject-rtos/zephyr · GitHub. The frequency of 12.5KHz is configured in code as shown in the image below

 

Altering this frequency has no effect on the speed of transmission when viewed with a Logic Analyzer. I would like to adapt the program to utilize the maximum SPI frequency available to me on the board, which is 32MHz. 

Also, if I try to use the Kconfig to add the option for a High Frequency Clock, the option is not available to be selected as seen below:

nRF Connect SDK Version: 2.1.0

Zephyr version: 3.1.99 

[Susheel Nuguru]

I have not tried the SPI bitbanging sample, but I am quite certain that bit banging is a slow process and will take many CPU cycles to bang just one bit of the serial protocol. I have not profiled this serial communication but 12.5Khz could be on the max end of what you can achieve with bit banging for SPI. I cannot say it for sure, since I have not tested this but I do not think you can achieve very high rates compared to 32MHz HFCLK.

[Jeff Maigemu]

Thanks for your reply. How would you suggest that I configure my SPI to achieve the maximum rates then?

[Simonr]

Hi

Susheel is out of office for the Easter holiday, and will get back to you on April 11th. Thank you for your patience!

Best regards,

Simon

[Susheel Nuguru]

Bitbanging does not go well with throughput achieved on embedded cores. Why wont you use an actial SPI peripheral that comes with our SoC?

[Jeff Maigemu]

I am currently looking to implement this. Please point me to some examples I could use as a reference