nRF51822 VDD_PA and dipole antenna

[pat]

I am the digital pcb and fw designer on a project using a dipole antenna defiend by the RF designer ( I have read the posts discouraging that and have taken that into account). Does the VDD_PA signal need to be fedback into ANT1 and ANT2 when using a balanced design? There is not much detail in the spec on this pin.

[adamvn]

Did you ever get a response for this?

[pat]

No, I never did. What we did was put a 0.022UF cap from VDD_PA to GND, a 39nH L from VDD_PA to ANT1, a 39nH L from ANT1 to ANT2. 0.022uF AC coupling on ANT1 and ANT2

[adamvn]

Thanks for the quick response, glad to know this. And it worked? And from there did you do some differential filtering/matching.

[pat]

Yes it worked. Basically the circuit described is the matching for us. Again, I wasn't the RF person on that.

[kelvin23]

Hi,

May I ask if the dipole antenna is a balanced port or the single-ended port? And what is the port impedance of the antenna, 50 or 15+j88? Thanks.