Does hardware control SPIS MISO Pin?

asked 2017-04-21 18:04:32 +0100

I've run into some interesting behaviour in my code and wanted to see if anyone can clarify for me. It seems as though the SPIS module doesn't set the MISO pin as high impedance when the CSN pin is deassertted as the documentation on the infocenter suggests.

From the SPIS section of the infocenter: "The MISO line is set in high impedance as long as the SPI slave is not selected with CSN."

What appears more correct is that the SPIS module will put the MISO pin state back to whatever settings are in the GPIO register when the CSN pin is deasserted.

I encountered this behaviour because I had called "nrf_drv_spis_init(...)" from the SDK - which sets the MISO pin as an input. Immediately after that in my code I set the direction to output and high drive strength - expecting that the MISO line would be 'set in high impedance as long as the SPI slave is not selected with CSN' as the infocenter stated. What I saw instead is that the MISO pin actually got driven from that point forward, whether or not CSN was asserted - it never got set to high impedance.

I would suggest that the wording in the infocenter documentation be changed to reflect the real behaviour of the pin, because as it is now it appears misleading. Or perhaps this is errata and the MISO pin was actually supposed to be forced to be an input when CSN was deasseted. Which is it?

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bjorn-spockeli gravatar image

answered 2017-04-24 15:53:20 +0100

updated 2017-04-25 08:18:21 +0100

Configuring a GPIO pin on the nRF52 to an input with no pull resistor corresponds to a high impedance GPIO pin. My question is why you set the MISO pin as an output after calling nrf_drv_spis_init(...)? The documentation states that To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO peripheral as described in Table 2 before enabling the SPI slaveimage description

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Fair point. I missed the sentance where it also states "This configuration must be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI master". Thanks for your response!

Corey Bird ( 2017-04-24 17:24:01 +0100 )editconvert to answer

Happy to help :)

Bjørn Spockeli ( 2017-04-25 08:18:43 +0100 )editconvert to answer

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Asked: 2017-04-21 18:04:32 +0100

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Last updated: april 21 '17