Does the nrf51 ARM M0 implement LDREX?

[donbluetooth]

The nrf51 ARM Cortex-M0 processors, according to the documentation, are "code compatible with Cortex-M3". Does this mean they implement LDREX/STREX instructions for atomic operations? These instructions are generally not implemented on M0 due to the architecture difference.

Thanks!

[Håkon Alseth]

Hi,

It's the other way around. M3 is code compatible with M0, not M0 is code compatible with M3.

From ARMs docs:

The ARMv7 architecture added these to the Thumb instruction set in the A and R profiles. ARMv7-M supports the byte and halfword but not the doubleword variants. ARMv6-M does not support exclusive accesses.

Cortex M0 is based on the ARMv6-m, as listed here.

Cheers, Håkon

[donbluetooth]

Hello,

I realize that the M0 is based on the ARMv6-M architecture. But, your own documentation states the following, from nRF51822 Product Specification v3.1 (section 3.1: CPU):

"""

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM Cortex-M processor series is implemented and available for M0 CPU. Code is forward compatible with ARM Cortex M3 based devices.

"""

Since code is "forward compatible" I was hoping that you magically implemented ldrex/strex. In what way is the M0 used on the nrf51 "forward compatible" with the M3?

Thanks,

[Håkon Alseth]

Hi,

This means that binaries compiled for the Cortex M0 will be compatible with the Cortex M3/M4. A binary compiled for M3/M4 will not be compatible with the M0 core.

It's the Cortex M3/M4 which has the full thumb instruction set, vs. the Cortex M0 which only has partial thumb: en.wikipedia.org/.../ARM_Cortex-M

Cheers, Håkon

[donbluetooth]

Ahh, now I understand how that statement should be read. Thanks for clarifying, Håkon.

[Petter Myhre]

@donbluetooth You can accept Håkon's answer by clicking the grey circle next to i.