Does the nrf51 ARM M0 implement LDREX?

[donbluetooth]

The nrf51 ARM Cortex-M0 processors, according to the documentation, are "code compatible with Cortex-M3". Does this mean they implement LDREX/STREX instructions for atomic operations? These instructions are generally not implemented on M0 due to the architecture difference.

Thanks!

[Håkon Alseth]

Hi,

It's the other way around. M3 is code compatible with M0, not M0 is code compatible with M3.

From ARMs docs:

The ARMv7 architecture added these to the Thumb instruction set in the A and R profiles. ARMv7-M supports the byte and halfword but not the doubleword variants. ARMv6-M does not support exclusive accesses.

Cortex M0 is based on the ARMv6-m, as listed here.

Cheers, Håkon

[Håkon Alseth]

Hi,

This means that binaries compiled for the Cortex M0 will be compatible with the Cortex M3/M4. A binary compiled for M3/M4 will not be compatible with the M0 core.

It's the Cortex M3/M4 which has the full thumb instruction set, vs. the Cortex M0 which only has partial thumb: en.wikipedia.org/.../ARM_Cortex-M

Cheers, Håkon