Understanding changes in NVIC registers as interrupt is raised

[morpho]

When an interrupt is raised, doesn't the peripheral's bit in a ISPR get set, which should be manually cleared in the ICPR?

For UART0, I see the following bits getting modified.

ISPR0 and ICPR0 seem to get modified to 0 but I'd expect the bit in ISPR to be set and ICER0 to yet to be set (should be done in the interrupt handler no)? Are these registers set somewhere in nordic lower layer prior to reaching UARTE0_UART0_IRQHandler (though I don't see in the call stack)?

Secondly, in STM32 they call it EXTI but here, INTENSET is somewhat similar in the sense that it's connected to NVIC? Ans of course NVIC register ISER would need to be set in addition to iNTENSET 

[Vidar Berg]

Hi,

Yes, when an interrupt is raised, it will be indicated as pending in the ISPR register. However, the pending status will be automatically cleared as soon as the program returns from the Interrupt Service Routine (ISR). Correction: the pending bit is cleared when entering the ISR. The ICPR register may be used to clear a pending interrupt when it has been disabled or masked.

(should be done in the interrupt handler no)?

You are only supposed to clear the peripheral event registers. The ISPR bits are cleared in HW.

INTENSET is somewhat similar in the sense that it's connected to NVIC

The INTENSET register is used to connect a peripheral event to the NVIC as shown by the picture here:

Peripheral interface

Best regards,

Vidar

[morpho]

Fair, so it's the peripheral register that needs to be cleared out and the NVIC registers are already taken of.

Regarding the delay following the clearing of an interrupt, it's upto 4 cycles but an interrupt may reoccur immediately within 4 cycles even if the new event hasn't come. I don't get the note to avoid the interrupt from reoccurring part... it says a read should be performed from the peripheral register but goes on to provide an example of clearing an event register or disabling the interrupt from the INTERCLR register. But aren't we already clearing an interrupt off the iNTERCLR register within the interrupt handler anyway?

[Vidar Berg]

If the peripheral event register is not cleared by the time the program exits the interrupt handler, the same interrupt will be triggered again, and you wouldn't want the same event to trigger multiple interrupts.

The note suggests performing a (dummy) read from one of the peripheral registers after clearing the event register to ensure that the write operation has taken place before exiting the interrupt handler. This read operation will act as a barrier, preventing the program execution from continuing until the write operation (i.e., writing '0' to the event register) is completed.

morpho said:

But aren't we already clearing an interrupt off the iNTERCLR register within the interrupt handler anyway?

INTENCLR is used to disconnect peripheral event signals from the NVIC when you no longer want the peripheral events to trigger interrupts.

void UARTE0_UART0_IRQHandler(void)
{
    if (NRF_UARTE0->EVENTS_RXDRDY == 0)
    {
        NRF_UARTE0->EVENTS_RXDRDY = 0;
        /* Dummy read*/
        uint32_t dummy = NRF_UARTE0->EVENTS_RXDRDY;
    }
}