Does Zephyr SPI APIs support two chip select pins?

I would like to use Zephyr SPI APIs (docs.zephyrproject.org/.../spi.html) to control external ADCs. Since I need two chip select pins for selection ADC1, ADC2, ADC3, and ADC4. Does Zephyr SPI APIs support two chip select pins?

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  • Hi

    There is no problem with multiple external ADC, you just need to set them up in a overlay. 

    This is described https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/zephyr/build/dts/api/bindings/spi/nordic,nrf-spi.html

    An array of chip select GPIOs to use. Each element
    in the array specifies a GPIO. The index in the array
    corresponds to the child node that the CS gpio controls.
    
    Example:
    
      spi@... {
              cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
                            <&gpio1 10 GPIO_ACTIVE_LOW>,
                            ...;
    
              spi-device@0 {
                      reg = <0>;
                      ...
              };
              spi-device@1 {
                      reg = <1>;
                      ...
              };
              ...
      };
    
    The child node "spi-device@0" specifies a SPI device with
    chip select controller gpio0, pin 23, and devicetree
    GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
    controller gpio1, pin 10, and flags GPIO_ACTIVE_LOW. Additional
    devices can be configured in the same way.
    
    If unsure about the flags cell, GPIO_ACTIVE_LOW is generally a safe
    choice for a typical "CSn" pin. GPIO_ACTIVE_HIGH may be used if
    intervening hardware inverts the signal to the peripheral device or
    the line itself is active high.
    
    If this property is not defined, no chip select GPIOs are set.
    SPI controllers with dedicated CS pins do not need to define
    the cs-gpios property.

    You can see below how it was done on the thingy91 with two different accelerometers on the same SPI bus 

    &spi3 {
    	compatible = "nordic,nrf-spim";
    	status = "okay";
    	cs-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>, <&gpio0 7 GPIO_ACTIVE_LOW>;
    
    	pinctrl-0 = <&spi3_default>;
    	pinctrl-1 = <&spi3_sleep>;
    	pinctrl-names = "default", "sleep";
    	adxl362: adxl362@0 {
    		compatible = "adi,adxl362";
    		spi-max-frequency = <8000000>;
    		reg = <0>;
    		int1-gpios = <&gpio0 9 0>;
    	};
    
    	adxl372: adxl372@1 {
    		compatible = "adi,adxl372";
    		spi-max-frequency = <8000000>;
    		reg = <1>;
    		int1-gpios = <&gpio0 6 0>;
    	};
    };

    Regards

    Runar

  • No worries, happy to help. I will just set this case to closed if that is okey with you? 

    Regards

    Runar

  • Thanks for your reply! Now I encounter another problem. From sample you provided, there are two SPI chip select pins (gpio0,8 and gpio0,7). How can I control SPI chip select for selecting adxl362 or adxl372?

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