SPI optimization

[valdev]

Hello I want to optimize SPI com as fast I can do: First I am using the fast spi data rate by SPI_FREQUENCY_FREQUENCY_M8 variable and I want to reduce at first the timing between the falling Chip Select edge and my first clock tick, and of course reduce the timing between the last clock tick and the rising Chip Select rising edge ...how can I process? Thanks!

[EDJ]

Hello: there are NORDIC drivers that are good but somewhat heavy in their overhead. The drivers employ software FIFOs, critical sections, etc. If you are sending a small number of bytes, and can wait for the transfer to complete, then it can be much faster to assert chip select, write 2 bytes to the SPI data register (it is double buffered), wait for two bytes to come back, and repeat until your transfer is done; then de-assert CS. Do this with interrupts enabled so that RF processes and timers can continue to run. You can still use the SPI driver init function, but disable ints from the SPI port after initializing, since you will be polling.

Also, it helps to have a logic analyzer on the SPI port; you can infer from that where the SW delays reside.

[valdev]

Thanks I gonna work on it!