Timing of SPI when sharing common lines on independent timers

[SG1]

We are using two SPI masters (SPIM0 and SPMI1) inside two independently running timers. SPIM0 and SPIM1 share MISO, MOSI, and SCK. Only the chip selects are different between the two. My question is as follows:

What will happen if the timers synchronize at some point and both try to access SPIM0 and SPIM1 t the same time? Does the chip schedule the order or will there be a conflict?

Thank you

[nordicator_prim3]

SPIM0 and SPIM1 should not share any pins. It sounds like you want to access 2 different slave devices. Both devices can be under SPIM0 and use different chip selects. The chip select is not defined for SPIM0, it is only assigned for each slave device on that bus.

I was assuming you're using Zephyr but in hindsight that may not be the case.
Example:

&spi2 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	sck-pin = <0>;
	mosi-pin = <1>;
	miso-pin = <6>;
	cs-gpios = <&gpio0 24 GPIO_ACTIVE_LOW>, <&gpio0 13 GPIO_ACTIVE_LOW>;

	sdhc0: sdhc@0 {
		compatible = "zephyr,mmc-spi-slot";
		reg = <0x0>;
		status = "okay";
		spi-max-frequency = <8000000>;

		mmc {
			compatible = "zephyr,sdmmc-disk";
			status = "okay";
			label = "SDMMC_0";
		};
	};

	// Wifi chip
	rs9116: rs9116@1 {
		status = "okay";
		compatible = "silabs,rs9116";
		reg = < 0x1 >;
		spi-max-frequency = <8000000>;
	};
};

[hmolesworth]

I would suggest the two SPI peripherals can indeed share SCK, MOSI and MISO pins, assuming two SPI peripherals are required by the application due to very different SPI settings or simple lack of spare io pins.

"The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as long as
the SPI master/slave is enabled, and retained only as long as the device is in System ON mode". TWIM is similar.

So the pins can be shared provided each SPI is disabled before using the other. However, they cannot occupy the same timeslot, which I think was the original question; some form of software lock would be required to avoid being enabled simultaneously. There is no chip order or priority which can avoid this, unless the two SPI peripherals were only enabled in an interrupt of equal priority such that neither could interrupt the other and the entire Enable-transfer-Disable sequence would have to take place in that single interrupt context. That can be done by using two SWI software interrupts of low and identical priority triggered from either a timer interrupt handler (software) or PPI (hardware). The matching low interrupt priority for both SWIs is required to avoid distorting timers and stuff based on interrupts; stuff in main() will be blocked until SPI transfers complete, which may affect sleep/power calculations. All other actions via interrupts will safely interrupt both of these SWI handlers.

[nordicator_prim3]

I didn't consider that use case; good explanation! I learn a lot from reading your replies - I see you all over this forum.