Timing of SPI when sharing common lines on independent timers

[SG1]

We are using two SPI masters (SPIM0 and SPMI1) inside two independently running timers. SPIM0 and SPIM1 share MISO, MOSI, and SCK. Only the chip selects are different between the two. My question is as follows:

What will happen if the timers synchronize at some point and both try to access SPIM0 and SPIM1 t the same time? Does the chip schedule the order or will there be a conflict?

Thank you

[nordicator_prim3]

SPIM0 and SPIM1 should not share any pins. It sounds like you want to access 2 different slave devices. Both devices can be under SPIM0 and use different chip selects. The chip select is not defined for SPIM0, it is only assigned for each slave device on that bus.

I was assuming you're using Zephyr but in hindsight that may not be the case.
Example:

&spi2 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	sck-pin = <0>;
	mosi-pin = <1>;
	miso-pin = <6>;
	cs-gpios = <&gpio0 24 GPIO_ACTIVE_LOW>, <&gpio0 13 GPIO_ACTIVE_LOW>;

	sdhc0: sdhc@0 {
		compatible = "zephyr,mmc-spi-slot";
		reg = <0x0>;
		status = "okay";
		spi-max-frequency = <8000000>;

		mmc {
			compatible = "zephyr,sdmmc-disk";
			status = "okay";
			label = "SDMMC_0";
		};
	};

	// Wifi chip
	rs9116: rs9116@1 {
		status = "okay";
		compatible = "silabs,rs9116";
		reg = < 0x1 >;
		spi-max-frequency = <8000000>;
	};
};

[SG1]

Thank you,

I am not using Zephyr. 

If I do configure it as above, what will happen if the timer tries to write to both chips at once? Will it be scheduled or will there be a conflict?

[hmolesworth]

Conflict, everything will die including possibility of hardware output pin damage. The timer must be stopped from writing to both at once, see post above for some options.

Edit: As a bare minimum, use the SPI ENABLE register as a hardware semaphore; do not enable a new SPI transaction to another chip until this register is 0 (released, disabled); remember to disable the SPI (ENABLE = 0) after a transaction.