nrf5340 128MHz & SPI 32 MHz

[tcube]

Hello,

I need a SPI running at maximum SPI (32MHz).

My understanding is to have a 32 MHz SPI, I need a core running at 128MHz.

What is the correct way to configure the core clock: (Device Tree? KConfig? nrfx lib?

Thanks

[Håkon Alseth]

Hi,

 

SPIM4 is capable of running 32 MHz (regardless of CPU clock freq).

Here's one example from 7002-DK for enabling spi4 (with ext flash):

https://github.com/nrfconnect/sdk-nrf/blob/v2.5.1/boards/arm/nrf7002dk_nrf7001_nrf5340/nrf5340_cpuapp_common.dts#L162-L185

 

I need a core running at 128MHz.

You can enable this using the clock control subsys, and call it like this:

https://github.com/nrfconnect/sdk-nrf/blob/v2.5.1/samples/wifi/shell/src/main.c#L57-L62

 

Kind regards,

Håkon

[Simon Third]

Hi Hakon,

I've been able to get SPI4 running at 32MHz. But I had to make a couple of manual changes to the SPIM4 register settings manually.  It looks like the settings for max-frequency and rx-delay were not being set from the device tree settings.

I had to add this code to get higher than 16MHz running.  Without it the frequency was being set to 16MHz and the rx-delay=2.  A 30ns delay is way to much at 32MHz.

#include <nrfx_spim.h>

#ifdef NRF_SPIM_HAS_32_MHZ_FREQ
		printk("spi has 32MHz\n");
		nrf_spim_frequency_set(NRF_SPIM_INST_GET(4),  NRF_SPIM_FREQ_32M);
		nrf_spim_iftiming_set(NRF_SPIM_INST_GET(4), 0);
#endif

My project is using board nrf5340dk_nrf5340_cpuapp and SDK V2.5.1

My overlay for the SPIM4 setup is 

&spi4{
    compatible = "nordic,nrf-spim";
	status = "okay";
    rx-delay = < 0x0 >;
    max-frequency = <33000000>;
	cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
	w25q64jv: w25q64jv@0 {
		compatible = "jedec,spi-nor";
		size = <0x4000000>; //8MBytes
		spi-max-frequency = <33000000>;
		reg = <0>;
		jedec-id = [ ef 40 17 ]; 
		wp-gpios = <&gpio0 19 0>;
		hold-gpios = <&gpio0 16 0>;
	};
};

&spi4_default {
     group1 {
        psels = <NRF_PSEL(SPIM_SCK, 0, 17)>,
                <NRF_PSEL(SPIM_MISO, 0, 14)>,
                <NRF_PSEL(SPIM_MOSI, 0, 13)>;
        nordic,drive-mode = < 3 >;
    };
};
&spi4_sleep {
    group1 {
        psels = <NRF_PSEL(SPIM_SCK, 0, 17)>,
                <NRF_PSEL(SPIM_MISO, 0, 14)>,
                <NRF_PSEL(SPIM_MOSI, 0, 13)>;    
    };
};

which produces .dts output of 

spi4: arduino_spi: spi@a000 {
				compatible = "nordic,nrf-spim";
				#address-cells = < 0x1 >;
				#size-cells = < 0x0 >;
				reg = < 0xa000 0x1000 >;
				interrupts = < 0xa 0x1 >;
				max-frequency = < 0x1f78a40 >;
				easydma-maxcnt-bits = < 0x10 >;
				rx-delay-supported;
				rx-delay = < 0x0 >;
				status = "okay";
				cs-gpios = < &gpio0 0x12 0x1 >;
				pinctrl-0 = < &spi4_default >;
				pinctrl-1 = < &spi4_sleep >;
				pinctrl-names = "default", "sleep";
				w25q64jv: w25q64jv@0 {
					compatible = "jedec,spi-nor";
					size = < 0x4000000 >;
					spi-max-frequency = < 0x1f78a40 >;
					reg = < 0x0 >;
					jedec-id = [ EF 40 17 ];
					wp-gpios = < &gpio0 0x13 0x0 >;
					hold-gpios = < &gpio0 0x10 0x0 >;
				};
			};

Which looks to be correct for the what the driver would need to set up the peripheral correctly?

It is interesting to note that I could set the frequency lower than 16MHz with overlay changes.

There seems to be no difference in using either CONFIG_SPI, or CONFIG_SPI_NOR.

Thanks 

Simon

[Håkon Alseth]

Hi Simon,

 

Sorry, I forgot to mention this. SPIM4 is 32M capable with dedicated pins, as described here:

https://infocenter.nordicsemi.com/topic/ps_nrf5340/spim.html?cp=4_0_0_6_29_6#topic

https://infocenter.nordicsemi.com/topic/ps_nrf5340/chapters/pin.html?cp=4_0_0_8_0

 

You can see this in the source code as well:

https://github.com/zephyrproject-rtos/hal_nordic/blob/nrfx-3.0.0/nrfx/drivers/src/nrfx_spim.c#L399-L428

 

Kind regards,

Håkon

[Simon Third]

Hi Hakon,

I've just noticed that I'm not using the SPIM4 dedicated pins.  I'm using the QSPI pins P0.13, P0.14, P0.16. Everything seems to be working with this setup.  I wonder if the driver could be updated to support this? i.e. all the other high drive pins?

I had wired the NOR Flash to the QSPI pins for 2-Bit mode, but it appears the qspi driver only supports 4 bit mode.

(p_config->skip_gpio_cfg && p_config->skip_psel_cfg)

is true in my case which might explain why the frequency and rx-delay were not picked up from the device tree settings.

Regards

Simon

[Håkon Alseth]

Hi Simon,

 

QSPI supports both quad, dual, and single mode by declaring these in DT:

https://github.com/nrfconnect/sdk-zephyr/blob/v3.4.99-ncs1-2/dts/bindings/mtd/nordic,qspi-nor.yaml#L34-L55

 

Here's an example of them used for quad io operation:

https://github.com/nrfconnect/sdk-zephyr/blob/v3.4.99-ncs1-2/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts#L232-L234

 

Kind regards,

Håkon

[Simon Third]

Thanks Hakon,

I've got the qspi running in dual mode now.

My overlay changes are 

&qspi{
    status = "okay";
    /delete-node/ mx25r6435f@0;
    w25q64: w25q64jq@0 {
        compatible = "nordic,qspi-nor";
		reg = < 0x0 >;
        writeoc = "pp";
        readoc = "read2io";
        sck-frequency = < 33000000 >;
        jedec-id = [ EF 40 17 ];
        size = < 0x4000000 >;
    };
};
/ {
    aliases {
        
        /delete-property/ spi-flash0;
        qspi-flash64 = &w25q64;
    };
};

Simon

[Håkon Alseth]

Hi Simon,

 

Glad to hear that you got it working!

And thank you for sharing the updated and working setup.

 

Hope you have a wonderful weekend!

 

Kind regards,

Håkon