Reset pin behaviour

[Fennec]

On both the 51 and the 52, I believe the reset pin is active low, and should otherwise be tied to VDD?

The reason I am asking is that I failed to find this information specifically pointed out in the documentation. If I'm missing something, please point out under which section I could find this in the reference manuals for either of these products.

Thanks a tonne for your time. :)

[atune]

Yes it's active low. In addition the internal pull-up should be enabled when a pin is configured as a reset pin. (disclaimer: idk about nrf51 earlier revisions)

It's funny that it's not explicitly stated anywhere. The only real reference (at least in 52's case) to the fact is in p.100 of the nRF52 OPS

which implies that a) pulling the pin down resets the chip and b) the internal pullup is enabled (R = 13kOhm).

[Hung Bui]

Hi Fennec and Atune,

I agree that information about the reset pin is a little bit obscure. But yes, the pin is active low and internal pull up will be enabled if the pin is configured as reset pin (a reset needed after you have configured PSELRESET registers). We will try to improve the documentation.

For the nRF51, information about the internal pull up for the reset pin can be found at section 11.1 in the nRF51 Reference Manual.

[Fennec]

Thanks for your answer. :)

[Fennec]

Thanks for your answer. :)

And thank you for offering to improve the docs (which are otherwise excellent) on this subject!

[Dajgoro Labinac]

I've been looking for the same info for a good 20 mins in the docu and could not find it anywhere. Good thing this post is still around.