SPI mode 3 clock polarity incorrect, nrfConnect SDK 2.5.0

[narrowerband]

Hello,

I am working on talking to a SPI slave device using SPI mode 3, so CPOL = 1 and CPHA = 1.

It is currently a very minimalistic project for testing purposes.

I am using the zephyr API for doing a single SPI transceive.

The problem is that the clock polarity is incorrect when doing a transaction. After the SPI CS is pulled low by the SPI API, the clock polarity is still low. While it should be high in SPI mode 3. This causes a rising edge, where it is visible that the SPI API has some vague understanding of what SPI mode it should be, as it is then high for a short idle period.

The result is that the SPI slave is confused now, since a rising edge on the SCLK when CS is low means that it samples a bit.

During the transceive, the SPI CLK goes to a low idle state (seems to not comply to its configured SPI mode).

I am struggling to find a way to make the SCLK be high from the moment CS is low (or before, I don't need this GPIO for anything else, it can be always high when idle).

Relevent code:

proj conf

CONFIG_SPI=y

dtsi

	spi0_default: spi0_default {
		group1 {
			psels =	<NRF_PSEL(SPIM_MISO, 0, 30)>,
				    <NRF_PSEL(SPIM_MOSI, 0, 05)>,
				    <NRF_PSEL(SPIM_SCK, 0, 02)>;
		};
	}

dts

slave_spi: &spi1 {
    compatible = "nordic,nrf-spim";
    status = "okay";

    overrun-character = <0xFF>;

    pinctrl-0 = <&spi0_default>;
    pinctrl-1 = <&spi0_sleep>;
    pinctrl-names = "default", "sleep";

    cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;

    slave: q123@0 {
        label = "spi-slave-device";
        compatible = "vnd,spi-device";
        status = "okay";
        reg = <0>;
        spi-max-frequency = <4000000>;
    };
};

application code

#define SPI_OP_MODE3 (SPI_OP_MODE_MASTER | SPI_LINES_SINGLE | SPI_WORD_SET(8) | SPI_LOCK_ON | SPI_HOLD_ON_CS | SPI_MODE_CPHA | SPI_MODE_CPOL)
const struct spi_dt_spec spi_slave_mode3 = SPI_DT_SPEC_GET(DT_NODELABEL(slave), SPI_OP_MODE3, 0);

err = spi_transceive_dt(&spi_slave_mode3, &tx, &rx);

I hope I provided enough info. Your help would be much appreciated.

Kind regards.

[narrowerband]

Hello,

I think I found the root cause of this issue.

pinctrl_apply_state(spi0_pinctrl, PINCTRL_STATE_DEFAULT); // default

This line was executed during initialization. I was under the impression that setting the default pin state (again) was not changing anything, but it seems to be the cause of the SCLK in the wrong polarity.

Kind regards.

[Jared]

Alright, so now it displays the correct clock polarity?

regards

Jared

[narrowerband]

Yes it's as it should be now, high when CS goes down and remains high between read/write operations.