Hi
I want to know why flash memory access should be scheduled in between the protocol radio event? is there any relation between the flash access and radio opeartion physically ?
thanks
Hi
I want to know why flash memory access should be scheduled in between the protocol radio event? is there any relation between the flash access and radio opeartion physically ?
thanks
Some processing from the CPU is required to handle the radio events, but not much. The problem with that is that the CPU is halted during flash operations, see NVMC chapter in the reference manual. So the problem is not the radio itself, but the availability of the CPU.
ok thanks...
But the description of NVMC chapter says that CPU is halted when CPU tries to fetch the CODE/DATA from flash only. that is, if CPU tries to fetch the CODE/DATA from RAM, it says there is no halt.
is it right?
if then, is the flash acccess in radio operation only restricted when CPU is using the flash for fetching CODE/DATA ?
thanks
ok thanks...
But the description of NVMC chapter says that CPU is halted when CPU tries to fetch the CODE/DATA from flash only. that is, if CPU tries to fetch the CODE/DATA from RAM, it says there is no halt.
is it right?
if then, is the flash acccess in radio operation only restricted when CPU is using the flash for fetching CODE/DATA ?
thanks