SPIS (SPI Slave interface) Set Up and Hold Timings

[David Nix]

In evaluating whether the nRF52833 can connect to our host microprocessor as a SPI slave, I noticed the set up and hold times listed in the data book nRF52833_PS_v1.6 as:

- tSUCSN (CSN to CLK setup time) = 1000 nanoseconds minimum

- tHCSN IVLK to CSN hold time) = 1000 nanoseconds minimum

Most SPI peripherals that I've worked worth have significantly shorter minimum setup and hold minimums - more in the 80 to 100 nanosecond range. Our SPI hardware doesn't honor such long setup and hold times and can't be modified for longer setup and hold times.

Can anyone verify that these minimum timings are correct? Or can the nRf52833 acting as a SPI slave shorten these timings programatically?

[Håkon Alseth]

Hi,

 

Unfortunately, this is the timing limitations of the nRF52(833) SPIS module:

https://docs.nordicsemi.com/bundle/ps_nrf52833/page/spis.html#ariaid-title35

 

Kind regards,

Håkon

[David Nix]

May I ask a follow-up question, then? If we assert CS# continuously between bus transfers, will the nRf52833 SPI peripheral (SPIS) still work properly? That would eliminate any timing constraints related to our SPI controller. For example, after initializing the SPI bus, can we driver CS low and leave it low indefinitely - while transferring data as needed?

[Håkon Alseth]

Hi,

 

No, it will be locked until a transaction is complete (ie. CSN deasserts):

https://docs.nordicsemi.com/bundle/ps_nrf52833/page/spis.html#ariaid-title4

  

Kind regards,

Håkon

[David Nix]

Thank you for your prompt reply. Just to be clear, I was asking if the SPI controller (the host) could drive CSN low (assert) indefinitely. However, if I understand you correctly, the SPIS interface of the nRf52833 must detect a transition of the CSN driven by the SPI controller before it will allow a transfer. Is this correct?

[Håkon Alseth]

Hi,

 

David Nix said:

However, if I understand you correctly, the SPIS interface of the nRf52833 must detect a transition of the CSN driven by the SPI controller before it will allow a transfer. Is this correct?

This is correct.

 

Kind regards,

Håkon