SPIS with nRF54L15 with the current Development Kit

Hello ! 
I'm trying to adapt the code from the master-slave SPI example (https://github.com/too1/ncs-spi-master-slave-example) for my nRF54L15 development kit.

The master part runs smoothly, but when it comes to the slave, I get a linking error on build (undefined reference to `__device_dts_ord_72' ).

When I look in build/zephyr/include/generated.devicetree_generated.h, I have Node 72 =  /soc/peripheral@50000000/spi@c8000

When I look in build/zephyr/zephyr.dts, I have : 

			spi22: spi_slave: spi@c8000 {
				compatible = "nordic,nrf-spis";
				#address-cells = < 0x1 >;
				#size-cells = < 0x0 >;
				reg = < 0xc8000 0x1000 >;
				interrupts = < 0xc8 0x1 >;
				max-frequency = < 0x7a1200 >;
				easydma-maxcnt-bits = < 0x10 >;
				status = "okay";
				pinctrl-0 = < &spi_slave_default >;
				pinctrl-1 = < &spi_slave_sleep >;
				pinctrl-names = "default", "sleep";
				cs-gpios = < &gpio1 0x0 0x1 >;
				def-char = < 0x0 >;
			};

My .overlay file look like this : 

//Disable everything that could collide, test only
&spi20 {
    status = "disabled";
};

&spi21 {
    status = "disabled";
};

&spi30 {
    status = "disabled";
};

&i2c20 {
    status = "disabled";
};

&i2c21 {
    status = "disabled";
};

&i2c22 {
    status = "disabled";
};

&i2c30 {
    status = "disabled";
};

&uart30 {
    status = "disabled";
};

&uart22 {
    status = "disabled";
};

&spi22{
    status = "okay";
};


&pinctrl {
    spi_slave_default: spi_slave_default {
        group1 {
            psels = <NRF_PSEL(SPIS_MOSI, 1, 2)>,
                    <NRF_PSEL(SPIS_SCK, 1, 1)>,
                    <NRF_PSEL(SPIS_MISO, 1, 3)>;
        };
    };

    spi_slave_sleep: spi_slave_sleep {
        group1 {
            psels = <NRF_PSEL(SPIS_MOSI, 1, 2)>,
                    <NRF_PSEL(SPIS_SCK, 1, 1)>,
                    <NRF_PSEL(SPIS_MISO, 1, 3)>;
            low-power-enable;
        };
    };
};

spi_slave: &spi22 {
	compatible = "nordic,nrf-spis";
    status = "okay";
	max-frequency = <DT_FREQ_M(8)>;
    pinctrl-0 = <&spi_slave_default>;
    pinctrl-1 = <&spi_slave_sleep>;
    pinctrl-names = "default", "sleep";
	cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	def-char = <0>;
};

In my .conf file, I have enabled CONFIG_SPI and CONFIG_SPI_SLAVE.

the simplified main.c looks like this : 

#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>

#include <zephyr/logging/log.h>

#define SPI_SLAVE DT_NODELABEL(spi_slave)
const struct device *my_spi_slave;

static void spi_slave_init(void)
{
	my_spi_slave = DEVICE_DT_GET(SPI_SLAVE);
	if(!device_is_ready(my_spi_slave)){
		LOG_ERR("SPI master device not ready!");
	}
}

...

int main(void){
spi_slave_init();
}

Whenever I call spi_slave_init(), I have the error on build.
I tried using :

#if !DT_NODE_EXISTS(DT_NODELABEL(spi_slave))
#error "Invalid Node Identifier !"
#endif

But it builds correctly (without the spi_slave_init() line).

I also tried to build the same main.c with a nRF52 config by adapting the .overlay file, and it runs smoothly.

If anyone has a clue, I would appreciate this !
Have a good day,
Hugo

Parents Reply Children
  • At this point I didn't manage to see anything on my CLK or MOSI.
    I agree that it seems to be a CS problem. When I look in the register un DEBUG mode, it seems that it's inactive : 

    While the other pins are set correctly. But it seems really weird to me, because when I build for CS = gpio2 6, I can see it HIGH on the scope (whereas on gpio2 5, it's always LOW). The definition in my code is really basic, like the sample code provided

    #define SPI_MASTER DT_NODELABEL(spi_master)
    #define MY_SPI_MASTER_CS_DT_SPEC SPI_CS_GPIOS_DT_SPEC_GET(DT_NODELABEL(reg_my_spi_master))
    const struct device *my_spi_master;
    //SPI configs
    static struct spi_config spi_master_cfg = {
    	.operation = SPI_WORD_SET(8) | SPI_TRANSFER_MSB | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_OP_MODE_MASTER,
    	.frequency = 4000000,
    	.slave = 0,
    	.cs = {.gpio = MY_SPI_MASTER_CS_DT_SPEC, .delay = 0},
    };
    And I didn't touch the overlay file.
    Is there maybe any issue i'm not aware off regarding GPIO2 pins ? Or the selection of the CS pin ? I'm kinda new to Zephyr & nRF SOC so it's a little bit blury on this side.
    Thanks,

    Hugo

  • I forgot to ask if you tested it on a nRF54 on your side. It would be helpful to know if it works on yours. Plus, if I don't manage to use Zephyr API, I can still use nrfx drivers defined in the nordic SDK right ?

  • Hi thank you for your patience 

    I'm testing right now, I wonder if maybe the different domains are causing us a bit of confusion. I don't see anything wrong 

    As long as mx25r64: mx25r6435f@0 is disabled there should not be anything on P2 from what I can see. 

    Edit: I think this might be the issue since we did not see anything on the clk pin. 

    P1.03, P1.04 and P1.08 can be used for SPICLK.

    I will do another test tomorrow morning

    Regards

    Runar

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