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The relation for PIN reset and other reset

FACE@shibuya


Sorry for long sentence.

The nRF5340 document describes about the Reset.
This chip set have the POR. so, if POR function work, I don't need to use the PIN reset.
because POR and PIN reset is similar function.

Is this correct ?

 

We use the Rest IC to assert the PIN reset.

In this case, POR and PIN reset is both useable,

What does it work for the chip set ?

 

When the voltage supplies the chip set, the POR work to the chip set.

After that, the RESET IC deassert .(the PIN reset changes from “L” to “H”.)

Is it no problem to use the above sequence ?

Our evaluation product doesn’t work GPIO at the chip set.

However, when we change PIN RESET pin from “L” to “H” by hand forced, the GPIO work.

( However, the communication core look like working, because the communication to the BLE device can do.)

 

And your document describes the PIN Rest following.

“Similar to a power-on reset, the application core is started after the reset pin is deasserted. The networkcore is held in reset, see Network force off on page 57.”
In my understanding of “Network core is held”,

If the Network core is held, the product cannot communicate to another device.
(However, my evaltation product can comunicate.）

We think that this problem occurred by the Rest function. So, we asked you about the reset function.



By the way,

Which type is the Rest signal detected by level or Eged ?

Best regars,
T.Shibuya

Parents
  • 0

    Hi, 

    I am working on your case and will update it when I collect enough information. 

    Regards,
    Amanda H.

  • 0 in reply to Amanda Hsieh

    Hi,

    I will wait the your answer for updateed information about my issue and question.

    By the way,
    What the RESET circuit diagram dose you recommend ?
    Don't we need to use the PIN RESET function at the Power on ?


    Best regards,
    T.Shibuya

  • 0 in reply to FACE@shibuya

    Hi, 

    The nRF5340 document describes about the Reset.
    This chip set have the POR. so, if POR function work, I don't need to use the PIN reset.
    because POR and PIN reset is similar function.

    Is this correct ?

    While POR (Power-on Reset) and PIN reset have similar effects, they serve different purposes. POR is automatically triggered when the supply voltage reaches the required threshold, while PIN reset allows external control of the reset function. It's generally recommended to implement both for robust system design. 

    We use the Rest IC to assert the PIN reset.

    In this case, POR and PIN reset is both useable,

    What does it work for the chip set ?

    When both POR and PIN reset are implemented, the chip will reset if either condition is met. This provides redundancy and allows for external control of the reset function.

    When the voltage supplies the chip set, the POR work to the chip set.

    After that, the RESET IC deassert .(the PIN reset changes from “L” to “H”.)

    Is it no problem to use the above sequence ?

    No, I don't see the issue from that sequence. The chip will reset if either condition is met.

    Our evaluation product doesn’t work GPIO at the chip set.

    However, when we change PIN RESET pin from “L” to “H” by hand forced, the GPIO work.

    ( However, the communication core look like working, because the communication to the BLE device can do.)

    Do you mean the GPIO functionality doesn't work until manually toggling the PIN reset? Could you elaborate in more detail? 

    I think you see the communication after the application core releases the network core.  Application core resets implicitly result in the network core being held in Force-OFF.  The network core will be held in Force-OFF until the application core releases it using the NETWORK.FORCEOFF register.  For more information, see Network Force-OFF.

    If the Network core is held, the product cannot communicate to another device.
    (However, my evaltation product can comunicate.）

    Application core resets implicitly result in the network core being held in Force-OFF. The network core will be held in Force-OFF until the application core releases it using the NETWORK.FORCEOFF register.

    Could you check the value of the NETWORK.FORCEOFF register? 

    Which type is the Rest signal detected by level or Eged ?

    Let me check with the team and then back to you. 

    FACE@shibuya said:
    What the RESET circuit diagram dose you recommend ?

    Please refer to the nRF5340 Reset Control. 

    FACE@shibuya said:
    Don't we need to use the PIN RESET function at the Power on ?

    May I know the reasons why you don't need the PIN RESET? What are your concerns? 

    The Power-on reset stated, "The power-on reset (POR) generator initializes the system when the VDD supply voltage is above the power-on threshold." This means that the chip will reset and initialize properly using just the POR function when power is applied. The PIN RESET is an additional reset mechanism that can be used for external control of the reset function without cycling power to the entire system. During development and troubleshooting, PIN RESET provides an easy way to reset the chip without cycling power. This can significantly speed up the debugging process.

    Regards,
    Amanda H.

Reply
  • 0 in reply to FACE@shibuya

    Hi, 

    The nRF5340 document describes about the Reset.
    This chip set have the POR. so, if POR function work, I don't need to use the PIN reset.
    because POR and PIN reset is similar function.

    Is this correct ?

    While POR (Power-on Reset) and PIN reset have similar effects, they serve different purposes. POR is automatically triggered when the supply voltage reaches the required threshold, while PIN reset allows external control of the reset function. It's generally recommended to implement both for robust system design. 

    We use the Rest IC to assert the PIN reset.

    In this case, POR and PIN reset is both useable,

    What does it work for the chip set ?

    When both POR and PIN reset are implemented, the chip will reset if either condition is met. This provides redundancy and allows for external control of the reset function.

    When the voltage supplies the chip set, the POR work to the chip set.

    After that, the RESET IC deassert .(the PIN reset changes from “L” to “H”.)

    Is it no problem to use the above sequence ?

    No, I don't see the issue from that sequence. The chip will reset if either condition is met.

    Our evaluation product doesn’t work GPIO at the chip set.

    However, when we change PIN RESET pin from “L” to “H” by hand forced, the GPIO work.

    ( However, the communication core look like working, because the communication to the BLE device can do.)

    Do you mean the GPIO functionality doesn't work until manually toggling the PIN reset? Could you elaborate in more detail? 

    I think you see the communication after the application core releases the network core.  Application core resets implicitly result in the network core being held in Force-OFF.  The network core will be held in Force-OFF until the application core releases it using the NETWORK.FORCEOFF register.  For more information, see Network Force-OFF.

    If the Network core is held, the product cannot communicate to another device.
    (However, my evaltation product can comunicate.）

    Application core resets implicitly result in the network core being held in Force-OFF. The network core will be held in Force-OFF until the application core releases it using the NETWORK.FORCEOFF register.

    Could you check the value of the NETWORK.FORCEOFF register? 

    Which type is the Rest signal detected by level or Eged ?

    Let me check with the team and then back to you. 

    FACE@shibuya said:
    What the RESET circuit diagram dose you recommend ?

    Please refer to the nRF5340 Reset Control. 

    FACE@shibuya said:
    Don't we need to use the PIN RESET function at the Power on ?

    May I know the reasons why you don't need the PIN RESET? What are your concerns? 

    The Power-on reset stated, "The power-on reset (POR) generator initializes the system when the VDD supply voltage is above the power-on threshold." This means that the chip will reset and initialize properly using just the POR function when power is applied. The PIN RESET is an additional reset mechanism that can be used for external control of the reset function without cycling power to the entire system. During development and troubleshooting, PIN RESET provides an easy way to reset the chip without cycling power. This can significantly speed up the debugging process.

    Regards,
    Amanda H.

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