QSPI initialization error sdk v2.6.1

Hello 

I am trying to initialize qspi in a ".cpp" file and methods like  

PINCTRL_DT_DEFINE(QSPI_NODE); are giving me "out-of-order initializers are nonstandard in C++"
so I had to do this work around 

#include <zephyr/drivers/flash.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/storage/flash_map.h>
#include <nrfx_qspi.h>
#include <stdint.h>
/* Define QSPI node from devicetree */
#define QSPI_NODE DT_NODELABEL(qspi)

/* Hardcoded pin configuration */
static const pinctrl_soc_pin_t qspi_pins[] = {
    NRF_PSEL(QSPI_SCK, 0, 17), // SCK on P0.17
    NRF_PSEL(QSPI_IO0, 0, 13), // IO0 on P0.13
    NRF_PSEL(QSPI_IO1, 0, 14), // IO1 on P0.14
    NRF_PSEL(QSPI_IO2, 0, 15), // IO2 on P0.15
    NRF_PSEL(QSPI_IO3, 0, 16), // IO3 on P0.16
    NRF_PSEL(QSPI_CSN, 0, 18), // CSN on P0.18
};

/* Define the state for QSPI */
static const struct pinctrl_state qspi_pin_states[] = {
    {
        .pins = qspi_pins,
        .pin_cnt = ARRAY_SIZE(qspi_pins),
        .id = PINCTRL_STATE_DEFAULT,
    },
};

/* Define the pinctrl_dev_config for QSPI */
static const struct pinctrl_dev_config qspi_pinctrl_config = {
    .states = qspi_pin_states,
    .state_cnt = ARRAY_SIZE(qspi_pin_states),
};

/* Configure and initialize QSPI */
static int qspi_init(void)
{
    static const nrfx_qspi_config_t qspi_config = {
        .prot_if = {
            .readoc = NRF_QSPI_READOC_READ4IO,
            .writeoc = NRF_QSPI_WRITEOC_PP4IO,
            .addrmode = NRF_QSPI_ADDRMODE_24BIT,
        },
        .phy_if = {
            .sck_delay = 0x05,
            .dpmen = false,
            .spi_mode = NRF_QSPI_MODE_0,
            .sck_freq = NRF_QSPI_FREQ_DIV2,
        },
        .skip_gpio_cfg = true,
        .skip_psel_cfg = false,
    };
    int ret = pinctrl_apply_state(&qspi_pinctrl_config, PINCTRL_STATE_DEFAULT);
    if (ret < 0)
    {
        LOG_ERR("Failed to apply pinctrl state");
        return ret;
    }

    nrfx_err_t err = nrfx_qspi_init(&qspi_config, NULL, NULL);
    if (err != NRFX_SUCCESS)
    {
        LOG_ERR("QSPI initialization failed: %d", err);
        return -EIO;
    }

    LOG_INF("QSPI initialized");
    return 0;
}

int qspi_read(uint32_t address, void *data, size_t size)
{
    int ret = nrfx_qspi_read(data, size, address);
    if (ret != NRFX_SUCCESS)
    {
        LOG_ERR("QSPI read failed: %d", ret);
        return -EIO;
    }
    LOG_INF("QSPI read successful");
    return 0;
}

int qspi_write(uint32_t address, const void *data, size_t size)
{
    int ret = nrfx_qspi_write(data, size, address);
    if (ret != NRFX_SUCCESS)
    {
        LOG_ERR("QSPI write failed: %d", ret);
        return -EIO;
    }
    LOG_INF("QSPI write successful");
    return 0;
}

which builds just fine for me.

however it this method causes the firmware to hault exactly at this line 

is it a mistake in my initialization ? or does this just not work in cpp?
thank you for your time.
Parents
  • Hi,

    I do not immediately see why this should not work, and I do not see anything indicating an error in the screenshot. Looking at the screenshot it looks as if there is a breakpoint there, is that why it halted there? If not, what yave you found by debugging (perhaps start by what exactly is really the state when execution seems halted if it is not due to a breakpoint")?

  • Hello Eianor,

    right after that break point I reach this point

     

    I apologize for not clarifying this.
    and here is the call stack:

    it's just like you said the implementation seems fine but i thought it might had something to do with hardcoding the values of the pins.
    also this is the overlay i am using

     

    
    &qspi {
        status = "okay";
        pinctrl-0 = <&qspi_default>;
        pinctrl-1 = <&qspi_sleep>;
        pinctrl-names = "default", "sleep";
    
        akd1500: akd1500@0 {
            compatible = "nordic,qspi-nor";
            reg = <0>;
            writeoc = "pp4io";            // Page Program 4-IO write command
            readoc = "read4io";           // Fast Read 4-IO read command
            sck-frequency = <8000000>;      // 8 MHz
            jedec-id = [EF 40 18];
            size = <0x4000000>;           // Example size: 64 MB
            has-dpd;
            t-enter-dpd = <10000>;
            t-exit-dpd = <35000>;
        };
    };
    
    / {
        aliases {
            akd1500 = &akd1500;
        };
    };
    
    &spi4 {
        status = "disabled";
    };
    
    &i2c1 {
        status = "disabled";
    };
    
    // &uart0 {
    //     status = "disabled";
    // };
    
    &uart1 {
        status = "disabled";
    };
    
    &i2c0 {
        status = "disabled";
    };
    
    &spi0 {
        status = "disabled";
    };
    
    &spi1 {
        status = "disabled";
    };
    
    &spi2{
        status = "disabled";
    };
    
    &spi3 {
        status = "disabled";
    };
    
    &uart1 {
        status = "disabled";
    };
    
    &pwm0 {
        status = "disabled";
    };
    
    &pwm1 {
        status = "disabled";
    };
    
    &pwm2 {
        status = "disabled";
    };
    
    &pwm3 {
        status = "disabled";
    };
    

    I disabled everything other than the qspi i don't think anything is causing conflict with the pins. although, I did write a random jedec id and size because I didn't know what the real values are.
    and here is my prj.conf file 

    CONFIG_MAIN_STACK_SIZE=8192
    CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=8192
    
    CONFIG_CPP=y
    CONFIG_STD_CPP17=y
    CONFIG_EXTERNAL_LIBCPP=y
    CONFIG_GLIBCXX_LIBCPP=y
    CONFIG_CPP_RTTI=y
    # CONFIG_CPP_EXCEPTIONS=y
    CONFIG_LIBCXX_LIBCPP=y
    CONFIG_REQUIRES_FULL_LIBCPP=y
    
    CONFIG_NEWLIB_LIBC=y
    CONFIG_NEWLIB_LIBC_NANO=n
    CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y
    
    
    # CONFIG_SPI=y            # Enable SPI support
    CONFIG_SPI_NOR=y
    CONFIG_NORDIC_QSPI_NOR=y        # Enable SPI NOR flash support
    CONFIG_NRFX_QSPI=y
    CONFIG_PINCTRL=y
    
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=n
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
     
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y
    
    #RTT seiral
    CONFIG_UART_CONSOLE=n
    CONFIG_RTT_CONSOLE=y
    CONFIG_USE_SEGGER_RTT=y

Reply
  • Hello Eianor,

    right after that break point I reach this point

     

    I apologize for not clarifying this.
    and here is the call stack:

    it's just like you said the implementation seems fine but i thought it might had something to do with hardcoding the values of the pins.
    also this is the overlay i am using

     

    
    &qspi {
        status = "okay";
        pinctrl-0 = <&qspi_default>;
        pinctrl-1 = <&qspi_sleep>;
        pinctrl-names = "default", "sleep";
    
        akd1500: akd1500@0 {
            compatible = "nordic,qspi-nor";
            reg = <0>;
            writeoc = "pp4io";            // Page Program 4-IO write command
            readoc = "read4io";           // Fast Read 4-IO read command
            sck-frequency = <8000000>;      // 8 MHz
            jedec-id = [EF 40 18];
            size = <0x4000000>;           // Example size: 64 MB
            has-dpd;
            t-enter-dpd = <10000>;
            t-exit-dpd = <35000>;
        };
    };
    
    / {
        aliases {
            akd1500 = &akd1500;
        };
    };
    
    &spi4 {
        status = "disabled";
    };
    
    &i2c1 {
        status = "disabled";
    };
    
    // &uart0 {
    //     status = "disabled";
    // };
    
    &uart1 {
        status = "disabled";
    };
    
    &i2c0 {
        status = "disabled";
    };
    
    &spi0 {
        status = "disabled";
    };
    
    &spi1 {
        status = "disabled";
    };
    
    &spi2{
        status = "disabled";
    };
    
    &spi3 {
        status = "disabled";
    };
    
    &uart1 {
        status = "disabled";
    };
    
    &pwm0 {
        status = "disabled";
    };
    
    &pwm1 {
        status = "disabled";
    };
    
    &pwm2 {
        status = "disabled";
    };
    
    &pwm3 {
        status = "disabled";
    };
    

    I disabled everything other than the qspi i don't think anything is causing conflict with the pins. although, I did write a random jedec id and size because I didn't know what the real values are.
    and here is my prj.conf file 

    CONFIG_MAIN_STACK_SIZE=8192
    CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=8192
    
    CONFIG_CPP=y
    CONFIG_STD_CPP17=y
    CONFIG_EXTERNAL_LIBCPP=y
    CONFIG_GLIBCXX_LIBCPP=y
    CONFIG_CPP_RTTI=y
    # CONFIG_CPP_EXCEPTIONS=y
    CONFIG_LIBCXX_LIBCPP=y
    CONFIG_REQUIRES_FULL_LIBCPP=y
    
    CONFIG_NEWLIB_LIBC=y
    CONFIG_NEWLIB_LIBC_NANO=n
    CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y
    
    
    # CONFIG_SPI=y            # Enable SPI support
    CONFIG_SPI_NOR=y
    CONFIG_NORDIC_QSPI_NOR=y        # Enable SPI NOR flash support
    CONFIG_NRFX_QSPI=y
    CONFIG_PINCTRL=y
    
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=n
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
     
    CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y
    
    #RTT seiral
    CONFIG_UART_CONSOLE=n
    CONFIG_RTT_CONSOLE=y
    CONFIG_USE_SEGGER_RTT=y

Children
No Data
Related