Seeking more information on NRF52833 ADC, reference, and buffers

[jdub]

Hi,

We are developing a product which is reading RTDs and thermistors from the NRF52833's internal ADC. We're working on compensating for the intrinsic errors of the ADC and gain buffers and have some questions not covered in the product specifications.

Do the ADC gain buffers have offsets associated with them? The datasheet says the ADC has an intrinsic offset of ±2LSB @ 10bit res but doesn't mention whether there are voltage offsets associated with the buffers.

Is there any procedure to internally determine the ADC buffer gains? For example, connecting the buffer inputs directly to the reference voltage?

Can you provide any more detail on what the ADC's internal calibration routine does or what it accounts for?

Are there any details on how the ADC input buffer gain is implemented?

Are there any specs on channel isolation in sequential measurement mode?

Is there a spec for temperature drift of the VDDH/5 divider?

Thank you!

[jdub]

Also - any details on the accuracy of the internal VDD/4 divider which can be used as an ADC reference? We are also finding that when using the VDD/4 reference, our signals are much noisier. Any specs on that noise or advice for reducing it?

[jdub]

Another few questions/details:
- Is the VDDH/5 input only enabled when REG0 is on? I'm working on a device where VDDH and VDD are tied together. The 1% spec on the VDDH/5 divider is better than the 3% spec on the ADC's input gain buffers, so I have been trying to use the VDDH5 input. But it behaves like it's floating (the reading seems arbitrary and the value decreases with sample rate, implying a loading effect)

- Does the ADC sequence converter fail if you use the CH[X}.CONFIG register's RESP and RESN settings to set inputs at VDD/2 while setting CH[X}.PSEL and NSEL to Not Connected? I can take a valid measurement in this configuration if I sample as a one-off, but if I make this measurement part of a sequence the ADC never finishes.

[jdub]

Sorry, another question:

In Product Spec v1.7, section 6.21.2.3 (SAADC Scan mode) it says "The time it takes to sample all channels is less than the sum of the conversion time of all enabled channels. The conversion time for a channel is defined as the sum of the acquisition time tACQ and the conversion time tCONV."

Why is the total conversion time less than the sum of the channels? What is skipped? What is the expected conversion time?

Thanks

[ketiljo]

Do the ADC gain buffers have offsets associated with them? The datasheet says the ADC has an intrinsic offset of ±2LSB @ 10bit res but doesn't mention whether there are voltage offsets associated with the buffers.

1) The input buffer of the ADC has auto-zero for offset. The offset of the ADC core should be scaled with the gain. 

Is there any procedure to internally determine the ADC buffer gains? For example, connecting the buffer inputs directly to the reference voltage?

2) Only for VDD as reference. There is an undocumented TASKS_CALIBRATEGAIN that connects the input to VDD/4 and uses gain 1/4

Can you provide any more detail on what the ADC's internal calibration routine does or what it accounts for?

3) The offset shorts the ADC input, and then a digital feedback loop tunes a current DAC in the SAR comparator to compensate for the offset. The offset may introduce a noise component if the TASKS_CALIBRATEOFFSET is triggered often

Are there any details on how the ADC input buffer gain is implemented?

4) Sorry, no details, but it's a switched capacitor gain stage with high common mode rejection. 

Are there any specs on channel isolation in sequential measurement mode?

5) There is only one core ADC, the muxing is done through T-gates (transmission gate, pull down, transmission gate), so there should be very little cross coupling between channels. 

Is there a spec for temperature drift of the VDDH/5 divider?

6) No, but it's a resistive divider, as such, as long as the ADC input settles, should not change with temperature (although the resistors do change with temperature, the relative size does not). The ADC temperature coefficient will dominate.

jdub said:

Also - any details on the accuracy of the internal VDD/4 divider which can be used as an ADC reference? We are also finding that when using the VDD/4 reference, our signals are much noisier. Any specs on that noise or advice for reducing it?

7)  The noise that you're seeing is probably coming from VDD. There is a low pass filter inside the ADC, but that is in the MHz range. 

jdub said:

Is the VDDH/5 input only enabled when REG0 is on? I'm working on a device where VDDH and VDD are tied together. The 1% spec on the VDDH/5 divider is better than the 3% spec on the ADC's input gain buffers, so I have been trying to use the VDDH5 input. But it behaves like it's floating (the reading seems arbitrary and the value decreases with sample rate, implying a loading effect)

8) That does not matter. VDDH/5 divider goes to the input gain buffers. I'm not sure it's enabled without the 5V regulator is enabled.

jdub said:

Does the ADC sequence converter fail if you use the CH[X}.CONFIG register's RESP and RESN settings to set inputs at VDD/2 while setting CH[X}.PSEL and NSEL to Not Connected? I can take a valid measurement in this configuration if I sample as a one-off, but if I make this measurement part of a sequence the ADC never finishes.

9) You need to enable the PSEL/NSEL, but not connect them to anything. Try writing 0xFE to both.

jdub said:

In Product Spec v1.7, section 6.21.2.3 (SAADC Scan mode) it says "The time it takes to sample all channels is less than the sum of the conversion time of all enabled channels. The conversion time for a channel is defined as the sum of the acquisition time tACQ and the conversion time tCONV."

Why is the total conversion time less than the sum of the channels? What is skipped? What is the expected conversion time?

10) Not sure why it's written like this as it's very confusing. We expect the conversion time to be N x (TACQ + t_conv).

[jdub]

Thank you Ketil, I hope Nordic will public more details in the next version of the product spec :)