Seeking more information on NRF52833 ADC, reference, and buffers

[jdub]

Hi,

We are developing a product which is reading RTDs and thermistors from the NRF52833's internal ADC. We're working on compensating for the intrinsic errors of the ADC and gain buffers and have some questions not covered in the product specifications.

Do the ADC gain buffers have offsets associated with them? The datasheet says the ADC has an intrinsic offset of ±2LSB @ 10bit res but doesn't mention whether there are voltage offsets associated with the buffers.

Is there any procedure to internally determine the ADC buffer gains? For example, connecting the buffer inputs directly to the reference voltage?

Can you provide any more detail on what the ADC's internal calibration routine does or what it accounts for?

Are there any details on how the ADC input buffer gain is implemented?

Are there any specs on channel isolation in sequential measurement mode?

Is there a spec for temperature drift of the VDDH/5 divider?

Thank you!

[jdub]

Another few questions/details:
- Is the VDDH/5 input only enabled when REG0 is on? I'm working on a device where VDDH and VDD are tied together. The 1% spec on the VDDH/5 divider is better than the 3% spec on the ADC's input gain buffers, so I have been trying to use the VDDH5 input. But it behaves like it's floating (the reading seems arbitrary and the value decreases with sample rate, implying a loading effect)

- Does the ADC sequence converter fail if you use the CH[X}.CONFIG register's RESP and RESN settings to set inputs at VDD/2 while setting CH[X}.PSEL and NSEL to Not Connected? I can take a valid measurement in this configuration if I sample as a one-off, but if I make this measurement part of a sequence the ADC never finishes.