Seeking more information on NRF52833 ADC, reference, and buffers

Hi,

We are developing a product which is reading RTDs and thermistors from the NRF52833's internal ADC. We're working on compensating for the intrinsic errors of the ADC and gain buffers and have some questions not covered in the product specifications.

Do the ADC gain buffers have offsets associated with them? The datasheet says the ADC has an intrinsic offset of ±2LSB @ 10bit res but doesn't mention whether there are voltage offsets associated with the buffers.

Is there any procedure to internally determine the ADC buffer gains? For example, connecting the buffer inputs directly to the reference voltage?

Can you provide any more detail on what the ADC's internal calibration routine does or what it accounts for?

Are there any details on how the ADC input buffer gain is implemented?

Are there any specs on channel isolation in sequential measurement mode?

Is there a spec for temperature drift of the VDDH/5 divider?

Thank you!

Parents
  • Sorry, another question:

    In Product Spec v1.7, section 6.21.2.3 (SAADC Scan mode) it says "The time it takes to sample all channels is less than the sum of the conversion time of all enabled channels. The conversion time for a channel is defined as the sum of the acquisition time tACQ and the conversion time tCONV."

    Why is the total conversion time less than the sum of the channels? What is skipped? What is the expected conversion time?

    Thanks

  • Do the ADC gain buffers have offsets associated with them? The datasheet says the ADC has an intrinsic offset of ±2LSB @ 10bit res but doesn't mention whether there are voltage offsets associated with the buffers.

    1) The input buffer of the ADC has auto-zero for offset. The offset of the ADC core should be scaled with the gain. 

    Is there any procedure to internally determine the ADC buffer gains? For example, connecting the buffer inputs directly to the reference voltage?

    2) Only for VDD as reference. There is an undocumented TASKS_CALIBRATEGAIN that connects the input to VDD/4 and uses gain 1/4

    Can you provide any more detail on what the ADC's internal calibration routine does or what it accounts for?

    3) The offset shorts the ADC input, and then a digital feedback loop tunes a current DAC in the SAR comparator to compensate for the offset. The offset may introduce a noise component if the TASKS_CALIBRATEOFFSET is triggered often

    Are there any details on how the ADC input buffer gain is implemented?

    4) Sorry, no details, but it's a switched capacitor gain stage with high common mode rejection. 

    Are there any specs on channel isolation in sequential measurement mode?

    5) There is only one core ADC, the muxing is done through T-gates (transmission gate, pull down, transmission gate), so there should be very little cross coupling between channels. 

    Is there a spec for temperature drift of the VDDH/5 divider?

    6) No, but it's a resistive divider, as such, as long as the ADC input settles, should not change with temperature (although the resistors do change with temperature, the relative size does not). The ADC temperature coefficient will dominate.

    jdub said:
    Also - any details on the accuracy of the internal VDD/4 divider which can be used as an ADC reference? We are also finding that when using the VDD/4 reference, our signals are much noisier. Any specs on that noise or advice for reducing it?

    7)  The noise that you're seeing is probably coming from VDD. There is a low pass filter inside the ADC, but that is in the MHz range. 

    jdub said:
    Is the VDDH/5 input only enabled when REG0 is on? I'm working on a device where VDDH and VDD are tied together. The 1% spec on the VDDH/5 divider is better than the 3% spec on the ADC's input gain buffers, so I have been trying to use the VDDH5 input. But it behaves like it's floating (the reading seems arbitrary and the value decreases with sample rate, implying a loading effect)

    8) That does not matter. VDDH/5 divider goes to the input gain buffers. I'm not sure it's enabled without the 5V regulator is enabled.

    jdub said:
    Does the ADC sequence converter fail if you use the CH[X}.CONFIG register's RESP and RESN settings to set inputs at VDD/2 while setting CH[X}.PSEL and NSEL to Not Connected? I can take a valid measurement in this configuration if I sample as a one-off, but if I make this measurement part of a sequence the ADC never finishes.

    9) You need to enable the PSEL/NSEL, but not connect them to anything. Try writing 0xFE to both.

    jdub said:

    In Product Spec v1.7, section 6.21.2.3 (SAADC Scan mode) it says "The time it takes to sample all channels is less than the sum of the conversion time of all enabled channels. The conversion time for a channel is defined as the sum of the acquisition time tACQ and the conversion time tCONV."

    Why is the total conversion time less than the sum of the channels? What is skipped? What is the expected conversion time?

    10) Not sure why it's written like this as it's very confusing. We expect the conversion time to be N x (TACQ + t_conv).

  • jdub said:
    Direct ADC question:
    The INL is listed as 4.7 bits, which is quite significant. Do you have any sense of whether the error at a given part of the transfer function is stable, or does it shift with time/temperature/supply voltage? Ie. Can we characterize the non-linearity for a given part and rely on that profile to calibrate future readings?

    In 12bit mode the INL is 4.7 LSBs, not bits. In 10-bit mode its around 1 LSB. The errors will likely be systematic. It is possible to compensate for some of the effects, however, it does require per device calibration. For example https://ieeexplore.ieee.org/document/7993659

    jdub said:
    Do you have any application notes related to reading a RTD or other high precision, low sensitivity resistance sensor?

    No, sorry

    jdub said:
    In our application we are very space constrained and must do so with a simple voltage divider setup, with a fixed resistor on top and temperature sensor on bottom. By taking differential measurements with the same gain settings across the different legs of the voltage divider, we can cancel out any tolerance errors on the references or gains of the ADC and buffers. But our final temperature reading still has more error than we expect, so we are trying to find ways to improve it.

    If you're using resistive input it's important that you select a TACQ that is long enough compared to the source impedance, see the product specification. 

  • > In 12bit mode the INL is 4.7 LSBs, not bits.

    You're right, that was just a typo on my part, I wasn't making my calculations with 2^4.7 = 26 LSB of noise Laughing

    > If you're using resistive input it's important that you select a TACQ that is long enough compared to the source impedance, see the product specification. 

    Yes our input impedance is <1kOhm which is very low, so we can use a short acquisition time. But we have found that extending it out to the maximum makes no difference on this measurement.

    Thank you!

  • The nRF52833 supports both 4-wire and 3-wire RTD modes on the SAADC, and the performance is better than the discussions above indicate. The trick is to use ratiometric measurements, and assuming no space for large S/H caps this can be done with a single reference resistor - typically mid-range say 2k0 - and a single 100nF capacitor (2 capacitors are better). Performance is within a few Ohms. No SAADC calibration is required due to the ratiometric measurement. 14-bit mode gives the best results, though 12-bit is almost as good. Sampling time of 10uSecs works fine, though if the remote lead length to the RTD is capacitive a longer setup time for the excitation may be required. Current is VDD dependent, but again ratiometric mode removes any issues with that.

    These results are using a noisy USB as power source; even better results if operating on a battery. This test is with current flowing from RTD to Reference and then reverse current through RTD and reference and the results would be averaged. Using both current directions removes long-term DC offset which avoids other issues. Current is off except during measurement.

    Edit: I decided to use two 100nF capacitors; if you have room on the board this improves the readings. I updated my schematic and code to clarify.

    This is a working design to produce these results:

    This code sample is designed to work with the schematic above on the nRF52833DK; I haven't bothered to optimise this code as it is already pretty quick and it is a simple proof-of-concept:

  • Interestingly I tested with both forward and reverse current and I see a bigger difference than expected. I'll update the previous post with the updated code. The results are very good for this ADC, better than expected.

    Edit: Performing an initial offset calibration removes the differences. I'll update results and code, this has been interesting. Edit 2: Tested reference and 2 test resistors on a 5-digit DMM, updated results

    Measured 14-bit value of 905.0 Ohm test resistor is 904.9 Ohms with -0.01% error

    Measured 14-bit value of 2984.6 Ohm test resistor is 2984.8 Ohms with  0.01% error

  • One last post, switching to floating-point to get accurate % error. Even with small averaging numbers looks very good, provided both forward and reverse current measurements are averaged to cater for residual SAADC offset.

    Measured value of 905.0 Ohm test resistor is 905.2 Ohms with 0.02% error in 12-bit mode <- Edit: got better results

Reply
  • One last post, switching to floating-point to get accurate % error. Even with small averaging numbers looks very good, provided both forward and reverse current measurements are averaged to cater for residual SAADC offset.

    Measured value of 905.0 Ohm test resistor is 905.2 Ohms with 0.02% error in 12-bit mode <- Edit: got better results

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  • Hi hmolesworth, sorry for the slow reply, I hope you had a good holiday.

    Thank you so much for running these experiments. I'm studying what you did and it aligns almost exactly with what we're doing. We use ratiometric measurements and are presently seeing about a ±2C spread in our final temperature values. This is roughly ±0.8ohm at the RTD. The resistance offset is consistent over time, and it varies from unit to unit. So one unit might be off by +0.4ohms consistently, another by -0.2ohms, another is dead on like your demo, etc.

    Main differences:

    - You are measuring both the reference resistor and RTD in differential mode. Due to the topology of our circuit, the RTD has one leg tied to GND, so it must be measured single-ended. I don't expect this to be significant.

    - You have a 4-wire RTD, our RTD is 2-wire but it's soldered to the same circuit board so the intermediate resistance should be small and constant.

    - We have a multi-microfarad cap in parallel with the RTD for noise suppression (I am presently investigating how much the soaking current could be throwing off our reading)

    - We adjust the PGA gain of the ADC for maximum dynamic range (although we are careful to keep the same PGA setting for the reference and RTD measurement)

    - The problematic measurements I'm seeing are on an extremely small form factor product. So creepage/clearance/leakage currents might be a factor here.

    So while I don't see a smoking gun that would account for the differences we see, I find your approach very reassuring, and it's leading me to believe I might be hunting an issue with the overall product/PCBA assembly, not the ADC intrinsically. Thank you again!

  • Good to hear from you, hopefully you got a good break.

    "The resistance offset is consistent over time, and it varies from unit to unit" is almost certainly a calibration issue, more about this below.

    "the RTD has one leg tied to GND, so it must be measured single-ended. I don't expect this to be significant" This is a huge issue, given that reversing the current flow allowing automatic residual offset compensation is not available. This means that SAADC calibration is essential, and the calibration must be performed at the same gain and sampling values as each measurement. SAADC offset calibration is known to be slightly dodgy, and must be repeated for any gain or temperature change. The best solution is to not tie the RTD to GND, unless the RTD itself is physically manufactured with a GND connection, in itself highly suspicious.

    "it's soldered to the same circuit board so the intermediate resistance should be small and constant" Pretty irrelevant, what matters is any common-mode current (current to/from other devices) using the same copper/vias as the RTD and reference resistor measurement. The SAADC, in addition, does not have a dedicated Gnd which makes things worse.

    "We have a multi-microfarad cap in parallel with the RTD" How many uF and what type? Any capacitor across the RTD requires an identical capacitor (repeat identical) across the reference; it can not be Tant or electrolytic and if ceramic must nave a voltage rating at least double the anticipated working voltage. Anything above 100nF is pointless; balanced capacitance on RTD and reference is much more important. Internal RTD capacitance must also be accounted for.

    "We adjust the PGA gain of the ADC for maximum dynamic range" The best performance (my opinion) is with gain at 1/6; anything higher degrades SAADC performance. Regardless, the SAADC calibration must be performed at the chosen gain as the SAADC offset changes with gain.

    "So creepage/clearance/leakage currents might be a factor" doubtful.

    Assuming the Gnd is fixed in the RTD and is immovable, use 3-wire sensing instead. I'll change my circuit to RTD Gnd and 3-wire and post the results and code later if I get time.

    As an endnote, ratiometric doesn't just mean comparing reference with RTD, but also comparing forward- and reverse-current measurements of reference and RTD since the SAADC (as with all ADCs) offsets are never really eliminated without doing this. Also it is often preferred to use VDD/4 and remove all capacitance across RTD and reference resistors to get true ratiometric results, regardless of reference voltage. In all cases, best to trigger the SAADC to start while the CPU and Radio are both quiet, a case for PPI.

    It would be helpful to see the front-end schematic and SAADC settings. Good luck :-)

  • I tested with 2-wire RTD and as expected the results are much poorer and vary from calibration to calibration as the residual offset is not handled. There are two ways to address that.

    Edit: 3 ways. I got quite good results by simply by alternating reversing the differential pin selection on the SAADC (no hardware change) to compensate for the residual SAADC offset: Updated results

    Measured 14-bit value of 905.0 Ohm 2-Wire test resistor using 128 samples is 904.9 Ohms with -0.01% error and much better stability/repeatability:

    The schematic/Circuit diagram:

    The code:

    So the (other) two ways to improve 2-wire results are to either have a separate differential channel to measure another calibration resistor in both forward and reverse current directions which allows calculation of the residual offset, and the best way I'll post separately with a schematic/circuit diagram as this post is getting a bit long. This last method gives the best results available for the SAADC in 4-wire or 2-wire mode (tomorrow maybe).

  • I updated the schematic on the previous post to include both P & N SAADC paths plus pin capacitance to explain the choice of 100nF.

    The final schematic/circuit diagram shows the use of flying capacitors to further isolate external influences and provide the option of using bias to re-center input voltages, which can now be beyond rail, for example at 11 volts. 2- and 3-wire modes require a triple SPDT and 4-wire mode requires a quad SPDT, although I would suggest using a quad SPDT as that converts 2- and 3-wire into 4-wire mode pretty well. If I get around to it I'll post some results.

  • I added the ENOB value for the 2-wire mode, looks pretty good though 4-wire still better; I'll test with the flying capacitors later this week.

    Measured 14-bit value of 905.0 Ohm 2-Wire test resistor using 128 samples is 905.1 Ohms with  0.02% error (12.6 ENOB)