How to properly configure GPIOTE PORT events

[sst_S.Sakamoto]

Hello,

I am using the following device and development kit:

• Device: NORA-B106-00B (nRF5340)
• nRF Connect SDK: 2.0.2

Currently, I am trying to use GPIOTE PORT events to detect interrupts on pins P0.04 and P0.28.

The mask for pins that do not use GPIOTE is defined in the Devicetree as follows:

&gpio0 {
	status = "okay";
	sense-edge-mask = < 0x10000010 >; //Mask GPIOTE events other than P0.04 and P0.28
};

Also, among the pins that mask GPIOTE events are the following pins used as SPIM4.

• P0.08/SCK
• P0.09/MOSI
• P0.10/MISO
• P0.11/CSN

I have PSRAM connected to SPIM4, which is turned off when idle and turned on when in use.

Here, if you try to write data using the nrfx spim driver after the power is turned on (P0.11/CSN:High), the write will not be executed as shown below, but if you read the data immediately after, the SPIM4 works and reads the data.

(Since no data has been written, the data read will be an undefined value.)

Also, even if you change the hardware to always have the PSRAM powered on (P0.11/CSN:Always High), the above procedure will not execute the first data write.

If you comment out "sense-edge-mask" in the Device Tree, the problem of this data not being written does not occur.

(It is possible that other pins are also behaving abnormally, but I have not been able to confirm this at present.)

Questions:

1. If I mask the GPIOTE event in Devicetree as above, could it affect other peripherals such as SPIM?
2. Is there another way to properly configure GPIOTE PORT events?

Best regard,

[Sigurd Hellesvik]

Hi

Which pins are you trying to configure with sense-edge-mask?

Is there another way to properly configure GPIOTE PORT events?

You can always use nrfx directly, as seen in this sample.

[sst_S.Sakamoto]

Hello,

Thank you for your reply.

I am trying to configure edge detection for P0.04 and P0.28 with sense-edge-mask.

I thought that I could mask the GPIOTE edge detection of other pins with the device tree settings above.

The sample you introduced does not seem to use sense-edge-mask, but is it correct to understand that if you configure GPIOTE only for the pins used for interrupts, there is no need to mask other pins?

Best regard,

[Jared]

Hi,

sst_S.Sakamoto said:

I understood that the registers will retain their settings as long as the system does not go to off.

Yes that is correct.

sst_S.Sakamoto said:

I will check these, so please wait.

ok!

sst_S.Sakamoto said:

Sorry, my explanation was insufficient.

Details of the SPIM signal line capture are shown below.

• sense-edge-mask enabled

• sense-edge-mask disabled

The SPIM communication processing operation is as follows:

Power on > SPIM write (SCK frequency:32MHz) > SPIM write and read (SCK frequency:16MHz)

From the above, we can see that when sense-edge-mask is enabled, the SPIM signal line is not output in the place where SPIM write should operate.

The colors of each line are correct as you said.

ah now I understand, thank you fort the clarification!

sst_S.Sakamoto said:

Please let me know if there is anything else to check.

I will continue to add information here if there is any progress.

If possible maybe you could provide a very simple example that reproduce the issue? Maybe something I can test on my development kit?

regards

Jared 

[sst_S.Sakamoto]

Hello Jared,

Sorry for the late reply.

I tried the method introduced in [135] SPIM: No output from SPIM4 at the link below:

[135] SPIM: No output from SPIM4

By implementing this procedure, I confirmed that the first SPIM4 write operation now works correctly even when sense-edge-mask is enabled.

If there is any official documentation or known errata about using this register in low-power scenarios, I would greatly appreciate any information you can provide.

Thank you very much for your help.

Best regards,

[Jared]

Hi,

We don't have any more information publicly available than what is already stated in errata. 

Great that it now works, maybe you can show me how you have implemented this errata and I can see if it's ok?

regards

Jared 

[sst_S.Sakamoto]

Hello Jared,

Thank you for your response. I’ve implemented the workaround based on the information provided in [135] (“SPIM: No output from SPIM4”). Below is an overview of how I applied the errata workaround in my code:

// Enable SPIM for PSRAM
*(volatile uint32_t *)0x5000ac04 = 1;
nrf_spim_enable(D_PSRAM_SPIM_PERIPHERAL);

// Disable SPIM for PSRAM
nrf_spim_disable(D_PSRAM_SPIM_PERIPHERAL);
*(volatile uint32_t *)0x5000ac04 = 0;

With these changes, the first write operation to external memory via SPIM4 now works consistently when the sense-edge-mask is enabled.

Could you please review this implementation and let me know if there’s any recommended improvement or best practice I might be missing?

Best regards,

[Jared]

Hi,

That looks correct,

regards

Jared