The question about GPIO port configuration sequence

[Eric158]

Is my following operation, first output high, and then configure as input, and then in the output low, this time in the output low here nrf_gpio_cfg_output(IO_PIN_C[j]); This one has a brief high level.

We look at the source routines are output and then write, so the understanding is nrf_gpio_cfg_output(IO_PIN_C[j]); Just configuration, the actual output level is after nrf_gpio_pin_write(IO_PIN_C[j],0) is executed. Is there a misunderstanding here?

[Jared]

Hi,

and then in the output low, this time in the output low here nrf_gpio_cfg_output(IO_PIN_C[j]); This one has a brief high level.

I tried replicating this but was not able to. 

After 

    nrf_gpio_cfg_input(IO_PIN[j], NRF_GPIO_PIN_PULLDOWN);

 

What voltage level do you see on the GPIO pin, is the pull down able to pull the voltage completely down to GND, or does it float a couple mV above that?

Is the GPIO connected to something externally? Do you observe the same if you cut the connection between the GPIO and the external part?

 

Can you share a screenshot of an oscilloscope that shows the voltage level?

regards

Jared 

[Eric158]

The voltage on the GPIO pin is 3.3V with a duration of about 800ns. This waveform still exists after disconnecting the external connection of GPIO. We suspect that when nrf_gpio_cfg_input is executed, the register value before the output high level is retained in the register, so there is this phenomenon.

  

[hmolesworth]

Correct behaviour, I'm afraid. The required output level (high or low) should be set before changing a pin to be an output pin; if the output level is set after making the pin an output pin the voltage level will be whatever was last set, as is the case here, and that voltage level will be held for one or more clock cycles at 16MHz plus any AHB-bus latency. This is not unusual or a bug, all CPUs and not just the nRF use a register for the output level on an output pin separate to the register which configures a pin to be input or output. Using a function for setting the output level and the configuration, as is the case in the code above, many 64MHz CPU cycles are added to the time taken to set the output level after setting the pin mode as the function traverses all the checking for developers. Best to use low-level, bare-metal, saves battery life but arguably not as safe.

Simple fix, always set the desired output level before setting output configuration, not after, especially when using functions.

[Eric158]

I think so too, but all of the SDK's sample code executes nrf_gpio_cfg_output() and then nrf_gpio_pin_write(). Does that mean the sample code is faulty?

[Jared]

Hi,

Thanks for providing the picture of the scope trace and making the issue clear. I agree with the comment from the other user in that this is an effect of configuring the direction of the pin first and then the voltage level. I would not call the sample code faulty as the product specification does not specify in which order you have to do this. 

regards

Jared