nRF54L AUX-AP access port description and usage

[Tomas Vanek]

Hi all,

In the PDF version of nRF54L PRELIMINARY DATASHEET v0.8, in chapter

9.1 Debug access port:

in table 65: Access port overview

is listed AUX access port of AHB-AP with AP ID 1.

Figure 160: Debug and trace overview

shows AUX-AP connected to VPR trough AMBIX0 block.

In table 66 in chapter 9.2 Access port protection:

Access port protection overview registers UICR.AUXAPROTECT, TAMPC.PROTECT.­AP[0].­DBGEN
are described as "These registers control the generation of the AHB-AP DBGEN signal,
which controls debug access to the VPR AHB-AP. This is used to provide debug capability for VPR."

But there is no other info where any VPR debugging resides in AUX-AP memory space.
Moreover I didn't find any readable address in AUX-AP.

FLPR/VPR RISC-V coprocessor DM (debug module) registers are exposed @ 0x4004C000 / 0x5004C000 of APP-AP (AP ID 0)  address space as described
in 8.26.1 Registers

What is AUX-AP for? Is possible to use it for RISC-V DM access?

[Tomas Vanek]

Sorry, I'm not asking about AP0 (APP CPU AP) address space. Yes, the RISC-V DM is mapped there. I quoted it in my first question

Tomas Vanek said:

FLPR/VPR RISC-V coprocessor DM (debug module) registers are exposed @ 0x4004C000 / 0x5004C000 of APP-AP (AP ID 0)  address space as described
in 8.26.1 Registers

and you replied

ketiljo said:

The main reason to have AP0 and AP1 (AUX-AP) to debug CM33 and VPR simultaneously using the corresponding APs. So the primary usage for AUX-AP is to use with RISC-V DM access as pointed in the question.

My question is how to use AP1 (AUX-AP) for RISC-V debugging? In the AUX-AP address space there is no DMSTATUS neither @ 0x44 nor @ 0x4004c444. And AFAIK no relevant info in the datasheet.

[ketiljo]

As far as VPR is concerned, it is accessed exactly same way in both AP0 and AP1, the RISC-V debugging registers are memory mapped to the address pointed above.

Tomas Vanek said:

In the AUX-AP address space there is no DMSTATUS neither @ 0x44 nor @ 0x4004c444

See the link in the last post, https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/vpr.html#ariaid-title14

[Tomas Vanek]

I rechecked it again. The registers are accessible on AP0 but NOT on AP1.

All ok on AP0:

> # UICR.AUXAPPROTECT[0].PROTECT0 and PROTECT1
> nrf54l.cpu mdw 0x00FFD040
0x00ffd040: ffffffff
> nrf54l.cpu mdw 0x00FFD05c
0x00ffd05c: ffffffff

> # TAMPC.PROTECT.AP[0].DBGEN.CTRL
> nrf54l.cpu mdw 0x500DC700
0x500dc700: 00000011

> # VPR.DEBUGIF.DMSTATUS
> nrf54l.cpu mdw 0x5004C444
0x5004c444: 00430c82

Just SWD FAULT responses on AP1:

> nrf54l.aux mdw 0x5004C444
Failed to read memory at 0x5004c444
> nrf54l.aux mdw 0x4004C444
Failed to read memory at 0x4004c444
> nrf54l.aux mdw 0x444
Failed to read memory at 0x00000444
> nrf54l.aux mdw 0x44
Failed to read memory at 0x00000044

It not of any help for me if you just repeat what I read several times. There must be an issue! But where?

[ketiljo]

The issue is possibly related to access violations. Could you share with us the AHB-AP CSW register configuration for both AP0 and AP1?

[Tomas Vanek]

Both AP0 and AP1 use OpenOCD default csw 0xa2000000