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Review PCB design for nrf54l15 for Matter over Thread use

Eric Xin

Hi, I would like to have some suggestions on my PCBA design for nrf54L15 chip. Please review it and give some suggestion moving forward. I am making this PCB to use this with matter-over-thread products. Since nrf54L15 is a pretty new product, I couldn't find many reference designs online. I mostly used the reference designs provided by Nordic but have been struggle on the programming port design. Also does nordic have any recommendation on which Antenna I should use for this design?

Thanks

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  • 0

    Hi Eric,

    I have reviewed the design. Just remember that 

    • "For the device to function properly, exposed die pad (pin 49) must be connected to ground (VSS, pins 32 and 44)".
    For programming external boards using the nRF54L15 DK's debug port, the external board must:

    Please let us know if you have any specific questions regarding programming the board.

    The rest of the design looks good.

    does nordic have any recommendation on which Antenna I should use for this design?

    Choosing the optimal antenna depends higly on the type of application, budget and available board space.

    • Monopole quarter wave PCB antenna: This is easy to make and tune, requiring only one shunt component for impedance matching plus the antenna length. It needs about 23 mm of space and a minimum 5 mm clearance to the ground plane. This is a good option if you have sufficient board space. Make the antenna a little longer than required and cut it shorter  on the prototype when tuning it. See General PCB design guidelines for nRF52 series.
    • Off-the-shelf chip antennas: There are many chip antennas available that work well with Nordic devices. These are particularly useful for size-constrained designs. When selecting a chip antenna, pay close attention to the recommended mounting instructions from the antenna vendor. Check out our reference designs Thingy:91/9X/53 for some examples.

    Nordic offers hardware reviews and tuning of the radio matching network and the antenna. Just create a private ticket on DevZone. 

    Also see nWP_017 - Antenna tuning.

  • 0 in reply to helsing

    Hi  

    Thanks for reviewing our PCB design! We have made the following changes.

    1. Make a 10-Pin SWD header
    2. Use a Monopole quarter wave PCB antenna

    Could you review our PCB layout and give some suggestions? We are especially worried about the Antenna performance. If you could provide some guidance in that front, that will be of great help.

    Thanks

    Eric

    design.PcbDoc

  • 0 in reply to Eric Xin
    Eric Xin said:
    design.PcbDoc

    Schematic review

    • Antenna matching components are missing. For a trace antenna, it is common to use one shunt component. Place the component close to where the trace antenna leaves the ground plane. Some designers use a Pi-network, however, one components could be enough.

    Layout review

    • Use a cut-out below the RF-path, in the to first layers.
    • Add a ground plane all the way along the cut-out in the two inner layers.
    • Keep a ground plane underneath the RF-path. Make sure there ground plane is continous in the area below the RF-path.
    • Do not route any signals below the RF-path unless there is a ground plane in between.
    • Copy the reference design layout 1:1 when it comes to placement of the radio matching circuitry. Pack the components as close together and as close to the nRF as possible.
    • C19, the 1.5 pF capacitor should be grounded to VSS_PA only. In other words, C19 should be grounded only to the SoC ground pad. This provides additional filtering. See the reference layout.
    • Use a 50Ohm coplanar waveguide in between the radio matching circuitry and the antenna matching circuittry. You may use some sw to calculate the trace width and you may ask the pcb manufacturer for the dielectric constant of your particular FR-4. See the mentioned General PCB design guidelines for nRF52 series for a note on coplanar waveguides.
    • The trace antenna needs 5mm clearance next to it. The ground plance marked with orange are too close. See nWP008 and the mentioned guidelines.
    • What is the gray dot next to the antenna? Avoid screews close to the antnena.
    • No copper should be below or above the antenna. See the blue ground plane marked with orange:
    • Vias are missing from the ground pad. Copy the 16 vias from the reference design.
    • Why is there no ground below U2? Have you doubled checked with the documentation or component manufacturer that this is recommended? You could in any case try to ask the manufacturer for a review.
    • Avoid noisy signals below the 32MHz crystal or crossing the XC1 and XC2 traces. Use a ground plane between the crystal and any traces.  
    • Use vias to ground on the top layer ground planes here:
    • Make sure use a vias to ground on any ground plane stubs to avoid having them radiate like little antennas. See suggested vias in green below. Consider removing the ground plane areas suggested with dark green, or ground these areas with a via to ground.
    • Remember to stitch vias to ground close to the cut-out and close to the RF-path.
    • Make sure to connect stubs in bottom layer ground to top layer ground as well, using the suggested vias in green, or remove the areas suggested in green:
    • Keep decoupling capacitors as close to the SoC as possible. (I have not checked this). See the reference layout.
Reply
  • 0 in reply to Eric Xin
    Eric Xin said:
    design.PcbDoc

    Schematic review

    • Antenna matching components are missing. For a trace antenna, it is common to use one shunt component. Place the component close to where the trace antenna leaves the ground plane. Some designers use a Pi-network, however, one components could be enough.

    Layout review

    • Use a cut-out below the RF-path, in the to first layers.
    • Add a ground plane all the way along the cut-out in the two inner layers.
    • Keep a ground plane underneath the RF-path. Make sure there ground plane is continous in the area below the RF-path.
    • Do not route any signals below the RF-path unless there is a ground plane in between.
    • Copy the reference design layout 1:1 when it comes to placement of the radio matching circuitry. Pack the components as close together and as close to the nRF as possible.
    • C19, the 1.5 pF capacitor should be grounded to VSS_PA only. In other words, C19 should be grounded only to the SoC ground pad. This provides additional filtering. See the reference layout.
    • Use a 50Ohm coplanar waveguide in between the radio matching circuitry and the antenna matching circuittry. You may use some sw to calculate the trace width and you may ask the pcb manufacturer for the dielectric constant of your particular FR-4. See the mentioned General PCB design guidelines for nRF52 series for a note on coplanar waveguides.
    • The trace antenna needs 5mm clearance next to it. The ground plance marked with orange are too close. See nWP008 and the mentioned guidelines.
    • What is the gray dot next to the antenna? Avoid screews close to the antnena.
    • No copper should be below or above the antenna. See the blue ground plane marked with orange:
    • Vias are missing from the ground pad. Copy the 16 vias from the reference design.
    • Why is there no ground below U2? Have you doubled checked with the documentation or component manufacturer that this is recommended? You could in any case try to ask the manufacturer for a review.
    • Avoid noisy signals below the 32MHz crystal or crossing the XC1 and XC2 traces. Use a ground plane between the crystal and any traces.  
    • Use vias to ground on the top layer ground planes here:
    • Make sure use a vias to ground on any ground plane stubs to avoid having them radiate like little antennas. See suggested vias in green below. Consider removing the ground plane areas suggested with dark green, or ground these areas with a via to ground.
    • Remember to stitch vias to ground close to the cut-out and close to the RF-path.
    • Make sure to connect stubs in bottom layer ground to top layer ground as well, using the suggested vias in green, or remove the areas suggested in green:
    • Keep decoupling capacitors as close to the SoC as possible. (I have not checked this). See the reference layout.
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