Sleep idle current for nRF52833XXAA.

[WFKwok]

I am testing the Sleep idle current for the nRF52833QDAA module.

The module is nothing connected outside except the fundamental circuit as the attached picture shown.

And I am using a very simple code to turn the module to sleep idle mode in the main.

here is the code:

void disable_ram_retention(void) {
    // Disable RAM retention for the desired RAM sections    
    // Add more sections as needed
    NRF_POWER->RAM[0].POWERCLR = 0; // Disable RAM section 0
    NRF_POWER->RAM[1].POWERCLR = 0; // Disable RAM section 0  
    NRF_POWER->RAM[2].POWERCLR = 0; // Disable RAM section 0
    NRF_POWER->RAM[3].POWERCLR = 0; // Disable RAM section 0
    NRF_POWER->RAM[4].POWERCLR = 0; // Disable RAM section 0
    NRF_POWER->RAM[5].POWERCLR = 0; // Disable RAM section 0
    NRF_POWER->RAM[6].POWERCLR = 0; // Disable RAM section 0
    NRF_POWER->RAM[7].POWERCLR = 0; // Disable RAM section 0
}

int main(void)
{
	disable_ram_retention();
    while (true) {		
         __WFE();  // Wait for event
		__SEV();
		__WFE();  // Wait for event again to ensure we stay in sleep mode
    }

}

void enable_ram_retention(void) {
    // Enable RAM retention for the desired RAM sections
    NRF_POWER->RAM[0].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[1].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[2].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[3].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[4].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[5].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[6].POWERSET = 1; // Disable RAM section 0
    NRF_POWER->RAM[7].POWERSET = 1; // Disable RAM section 0
}

I find that there is totally no sleep idle current difference if I called enable_ram_retention or disable_ram_retention before enter sleep idle mode.

So How can I achieve the sleep idle mode current ( System ON, no RAM retention, wake on any event 1.1uA) without RAM retention according to the nRF52833 manual?

Right now it is only average 2uA, any help to achieve 1.1uA??

Thanks.

[hmolesworth]

The ARM uses a set/reset architecture as well as the actual register whose bits are being set or reset, ie 3 register "addresses" mapped to the single 32-bit physical register. To set a bit write a '1' to the SET or a '1' to the actual; to reset write a '1' to the CLR or a '0' to the actual. Using the SET or CLR access registers allows write access to the bit without having to do the read-modify-write when changing a single bit. Hence the fix:

void disable_ram_retention(void) {
    // Disable RAM retention for the desired RAM sections    
    // Add more sections as needed
    NRF_POWER->RAM[0].POWERCLR = 1; // Disable RAM section 0
    NRF_POWER->RAM[1].POWERCLR = 1; // Disable RAM section 0  
    NRF_POWER->RAM[2].POWERCLR = 1; // Disable RAM section 0
    NRF_POWER->RAM[3].POWERCLR = 1; // Disable RAM section 0
    NRF_POWER->RAM[4].POWERCLR = 1; // Disable RAM section 0
    NRF_POWER->RAM[5].POWERCLR = 1; // Disable RAM section 0
    NRF_POWER->RAM[6].POWERCLR = 1; // Disable RAM section 0
    NRF_POWER->RAM[7].POWERCLR = 1; // Disable RAM section 0
}

Of course the stack should preferably not be in a RAM section being turned off although it's arguable whether the return to caller address would occur before the power to the stack ram was actually lost; normally the CLR would be in-line and not in a function call to avoid this potential race hazard.

[WFKwok]

Hi hmolesworth,

Have changed the fix as you suggested.
It does drop the sleep idle current from 2.1uA to 1.52uA.

However is it still possible to further reduce the current to the nrf52833 technical manual (1.1uA)??
By the way, there is a periodic pitch (20~30ms duration, current draw up to 6uA),
where does it come from? (HFCLK 32MHZ? can I config something to further optimize? like LFCLK)
Is there something that I can optimize?
Thanks!!

[hmolesworth]

Maybe try:

    NRF_POWER->RAM[8].POWERCLR = 1; // Disable RAM section 0

[WFKwok]

tried RAM[8] but does not help, keep no difference.

[hmolesworth]

Periodic pulse is likely the hysteretic mode of the internal regulators; this is affected by the value and type of external capacitors fitted; maybe review those against the recommended values and types.