nrf54l15 low-power domain

[Dr. Vegapunk]

According to the data sheet, the nrf54l05/10/15 has 4 power domains. And there is a low-power domain. I search through the entire datasheet for a few hours and still couldn't find why the low-power domain is low power (at least compared to peripheral domain) and how to utilize the low-power domain to achieve the lowest power. In fact, compared to peripheral domains, the only differences I can find are pretty much peripheral availabilities and that it runs asynchronously to the MCU domain. There are also languages for GPIO ports like:

P0 low-power domain – These I/O pins can wake the system up from System OFF or System ON sleep, and can be accessed by all peripherals in the low-power domain.
P1 peripheral domain – These I/O pins can wake the system up from System OFF or System ON sleep, and can be accessed by all peripherals in the peripheral domain.

that make the GPIO pins in these two domains functionality sound similar if not identical. They can both wake system up, so why use low-power domain vs peripheral domain? 

Can you some explain or give some direction to the right literature explaining this power domain architecture?

May the force be with you~

[Kenneth]

Hi,

The nRF54L15 features multiple power domains, including a fast MCU domain, a radio domain, a peripheral domain, and a low-power domain. Here’s how the power domain architecture is structured and how to utilize the low-power domain for optimal power efficiency:

1. Power Domains Overview:

   • Fast MCU Domain: Contains the Arm Cortex-M33 and high-speed peripherals. Runs at 128 MHz.
   • Radio Domain: Contains the short-range radio and supporting peripherals. It operates at 32 MHz, synchronously with the fast domain.
   • Peripheral Domain: Houses most peripherals, operating synchronously with the fast domain at 16 MHz.
   • Low-Power Domain: Comprises peripherals intended for ultra-low power mode applications. It operates asynchronously at 16 MHz compared to the fast domain.

2. Low-Power Domain Characteristics:

   • It's designed for peripherals used in ultra-low power modes. This domain can wake up the rest of the system even when other domains are powered off. It operates independently of the fast domain, allowing for reduced power consumption when high-speed operations are not required.
   • The low-power domain runs asynchronously, meaning activities in this domain do not require synchronization with high-speed tasks, which saves power in applications with sporadic, less timing-critical operations.
     
     

3. Utilizing the Low-Power Domain:

   • GPIO Functionality: GPIO pins in the low-power domain can wake the system from sleep modes (System OFF or System ON sleep). Although similar functionality is available in the peripheral domain, using the low-power domain helps conserve energy by only powering necessary components.
   • Configuring Power: When aiming for the lowest power, ensure minimal components in the high-frequency domains are active. Employ peripherals in the low-power domain for tasks not requiring high-speed computations.

For more detailed setup and configurations, refer to Power and Clock Management. This system evaluates requests and starts/stops clock sources to choose optimal regulator operation modes for efficiency. Additionally, see the GPIO Configuration for specific settings related to GPIO ports across different domains.

Hope that helps,
Kenneth