According to the data sheet, the nrf54l05/10/15 has 4 power domains. And there is a low-power domain. I search through the entire datasheet for a few hours and still couldn't find why the low-power domain is low power (at least compared to peripheral domain) and how to utilize the low-power domain to achieve the lowest power. In fact, compared to peripheral domains, the only differences I can find are pretty much peripheral availabilities and that it runs asynchronously to the MCU domain. There are also languages for GPIO ports like:
P0 low-power domain – These I/O pins can wake the system up from System OFF or System ON sleep, and can be accessed by all peripherals in the low-power domain.
P1 peripheral domain – These I/O pins can wake the system up from System OFF or System ON sleep, and can be accessed by all peripherals in the peripheral domain.
that make the GPIO pins in these two domains functionality sound similar if not identical. They can both wake system up, so why use low-power domain vs peripheral domain?
Can you some explain or give some direction to the right literature explaining this power domain architecture?
May the force be with you~