When the clock source is LFRC then the device goes into high power state which is ~800uA

[Gaurav]

I have my application running (NCS 2.6.4) on the bench with clock source set as internal RC and with the configurations such as -

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=y
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD=5000
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON=y
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP=10

But when I do multiple resets using nrfjprog --reset then the device goes into high power state which have the average current as ~800uA but the application runs normally and there is no issue in functionality.
When I switch the clock configuration to XTAL then the issue goes away which signifies there is some issue with the clock source and I am able to replicate the same state on the board with blinky example with the above clock configurations.

Any workaround which can solve this issue apart from changing the configuration to XTAL.

[Jared]

Hi,

Is there a chance that the device is still in debug mode when you test this? In debug mode the device will not enter IDLE sleep but will emulate it. Debug mode is activated when the debugger is connected, and disconnecting the debugger is not enough to exit debug mode. Only a power on reset will 100% exit debug mode, although I would have expected pin reset to have similar result.

regards
Jared 

[Gaurav]

Jared Yes the debugger was connected but the behaviour is very weird here as the device stays in high power state even in pin resets state.
For this to debug I have added to note down ramp up time of HFXO and this value was coming as 1uS for this scenario. And when I DFU or flash application with XTAL configured then the issue goes away.

[Jared]

Hi Gaurav,

I still suspect that this issue is related to the chip not going into sleep mode due to debug mode. How this is correlates to your observation with LFCLK source is not clear.

Do you have PPK2 that you can use to share a complete power trace with me that I can analyze? 

Are you supplying any other external circuitry trough VDD from the nRF52840? 

Here is an overview over the difference between soft reset and power-on-reset:

Also, I don't think it's unreasonable to require a power cycle to be performed after you have flashed the nRF52840 with an external debugger. 

regards

Jared

[Gaurav]

 Jared Sharing you the profile of PPK for the same

Jared said:

Do you have PPK2 that you can use to share a complete power trace with me that I can analyze? 

https://drive.google.com/file/d/1SzewOPLXNTN-MAdSXlwhM-6Sq5EOF-VZ/view?usp=drive_link

Jared said:

Also, I don't think it's unreasonable to require a power cycle to be performed after you have flashed the nRF52840 with an external debugger. 

Issue here is I can allow one power cycle but it goes into high power state again, and we cannot do power cycle everytime it goes into high power state

[Gaurav]

Jared Anything on the above

[Jared]

Hi,

Please upload the trace here, we can't access external sites such as the one that you have shared.

Drag-and-drop the zip into the reply box or use insert->Image/video/file

regards

Jared 

[Gaurav]