Controlling GPIO on a common port from two different cores

[Peter Langer Keysoft]

We have
nRF54H20DK (rev. 0.9.1), SDK: v2.9.0-nRF54H20-1 and the same Toolchain, IDE: VSCode + nRF Connect plugin

We need to control the GPIO LEDs from two cores (P9.00, P9.01 on the APP core and P9.02, P9.03 on the RAD core), i.e. on the same port - does this mean that the GPIO drivers on the cores must use the same memory? 

Here are the "overlapping" visualizations that indicate possible conflicts when all LED control is enabled on both cores.

Is this possible? If so, how do I need to configure the "overlay" and prj.conf files for both cores?

Br, KeySoft

[Kazi Afroza Sultana]

Hello,

The nRF54H20 is a multicore System-on-Chip (SoC) that uses an asymmetric multiprocessing (AMP) configuration. Each core is tasked with specific responsibilities and is optimized for different workloads. It is partitioned into functional blocks called ''Domains'' such as application, radio, secure, global etc. The domains containing the user-programmable main CPUs and associated functions are called Cores. 

 Most memory and peripherals can be flexibly allocated to cores at compile time. Most memory and peripherals can be flexibly allocated to cores at compile time.

P9 GPIO pins that can be configured for various functions.

Is this possible? If so, how do I need to configure the "overlay" and prj.conf files for both cores?

So, I think you should be able to control these pins independently from their respective cores without needing to share memory for the GPIO drivers.

I will show you the overlay part later.