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RF testing uart pin configuration issue

Sufaira N

Hi,

I am working on RF testing on the custom board.

I have configured the nrf UART TX in p1.04 and UART RX pin in p0.13.

UART TX pin is working fine, but the UART Rx is not working.

I tried on the NRF5340 DK, but it is not working on the DK either.

I need to use the p0.13 pin in my custom board.

In this project,

QSPI_IO0 is also using p0.13.So I commented the configuration of QSPI, which also didn't work.
What is the solution to configure the UART RX pin as p0.13?
Thank you.
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  • 0

    Hello,

    P0.13 is not connected to the pin header on the DK unless you have shorted the solder bridge mentioned here: https://docs.nordicsemi.com/bundle/ug_nrf5340_dk/page/UG/dk/hw_external_memory.html 

    QSPI_IO0 is also using p0.13.So I commented the configuration of QSPI, which also didn't work.

    In the devictree? Please show the configuration you commented out.

    Best regards,

    Vidar

  • 0 in reply to Vidar Berg
      I commented in 2 files
    1) In nrf5340_cpuapp_common_pinctrl.dtsi,

            // qspi_default: qspi_default {
            //      group1 {
            //              psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
            //                      <NRF_PSEL(QSPI_IO0, 0, 13)>,
            //                      <NRF_PSEL(QSPI_IO1, 0, 14)>,
            //                      <NRF_PSEL(QSPI_IO2, 0, 15)>,
            //                      <NRF_PSEL(QSPI_IO3, 0, 16)>,
            //                      <NRF_PSEL(QSPI_CSN, 0, 18)>;
            //              nordic,drive-mode = <NRF_DRIVE_H0H1>;
            //      };
            // };

            // qspi_sleep: qspi_sleep {
            //      group1 {
            //              psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
            //                      <NRF_PSEL(QSPI_IO0, 0, 13)>,
            //                      <NRF_PSEL(QSPI_IO1, 0, 14)>,
            //                      <NRF_PSEL(QSPI_IO2, 0, 15)>,
            //                      <NRF_PSEL(QSPI_IO3, 0, 16)>;
            //              low-power-enable;
            //      };
            //      group2 {
            //              psels = <NRF_PSEL(QSPI_CSN, 0, 18)>;
            //              low-power-enable;
            //              bias-pull-up;
            //      };
            // };             
                                    
    2) In nrf5340_cpuapp_common.dtsi 
    // &qspi {
    //      status = "okay";
    //      pinctrl-0 = <&qspi_default>;
    //      pinctrl-1 = <&qspi_sleep>;
    //      pinctrl-names = "default", "sleep";
    //      mx25r64: mx25r6435f@0 {
    //              compatible = "nordic,qspi-nor";
    //              reg = <0>;
    //              /* MX25R64 supports only pp and pp4io */
    //              writeoc = "pp4io";
    //              /* MX25R64 supports all readoc options */
    //              readoc = "read4io";
    //              sck-frequency = <8000000>;
    //              jedec-id = [c2 28 17];
    //              sfdp-bfp = [
    //                      e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
    //                      ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
    //                      10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 68 44
    //                      30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
    //              ];
    //              size = <67108864>;
    //              has-dpd;
    //              t-enter-dpd = <10000>;
    //              t-exit-dpd = <35000>;
    //      };
    // };
  • 0 in reply to Sufaira N

    Thanks for confirming. Commenting the lines you did will free up P0.13. Does RX work if you swap TX/RX or assign RX to another pin?

  • 0 in reply to Vidar Berg

    Thanks for the reply.

    Yes, it is working when I use other pins except p0.13, p0.14, p0.15 and p0.16.

  • 0 in reply to Sufaira N
    Sufaira N said:
    p0.13, p0.14, p0.15 and p0.16.

    Are all these pins accessible on your custom board?

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