nrf54L15 LFRC 32KHz clock configuration issue

[ppatel]

Hi,

We are trying to get our nRF54L15 running, but are running into clock issues. The hardware is configured without an external 32kHz crystal, so we want to rely on the NRF54's internal RC for our low-speed clock. We need to configure the GRTC to use the internal RC, not the external LFXO. We have set the following clock-related Kconfig options to accomplish this:

```
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_NRF=y

CONFIG_NRFX_CLOCK=y
CONFIG_NRF_GRTC_TIMER=y
CONFIG_NRF_GRTC_START_SYSCOUNTER=y
CONFIG_NRFX_GRTC=y
CONFIG_NRFX_CLOCK_LF_SRC_RC=y

CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=n
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=y
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON=y
```

We also have our device-tree set up as follows (relevant snippets):

```
#include <nordic/nrf54l15_cpuapp.dtsi>

&lfxo {
    status = "disabled";
    load-capacitors = "internal";
    load-capacitance-femtofarad = <7000>;
    clock-frequency = <32768>;
};

&hfxo {
    status = "okay";
    clock-frequency = <32000000>;
    load-capacitors = "internal";
    load-capacitance-femtofarad = <17000>; // 17pF per BM15C datasheet
};

&grtc {
    owned-channels = <0 1 2>;
    status = "okay";
};

&clock {
    status = "okay";
};

```

However, when we run our application with the debugger enabled, we are stuck in clock initialization -- in the GRTC initialization. github.com/.../nrfy_grtc.h. More precisely, we get stuck inside of the sys counter ready check. Upon inspecting the GRTC registers, we see that the GRTC is configured in CLKSEL to use the LFXO. However, it should be it should be configured to use the RC per my Kconfig options. I have verified from KConfig output that the necessary config options are enabled.

We are at a loss as to why the GRTC is not configured to use the RC, as it is explicitly set to do so in our configuration. Any help would be greatly appreciated.

[Hung Bui]

Hi PPatel, 

As far as I know you would need to remove the lfxo from the device tree. Please add this to an overlay file (app.overlay for example): 

/delete-node/ &lfxo;

grtc {
      /delete-property/ clocks;
      /delete-property/ clock-names;
      clocks = <&pclk>;
      clock-names = "hfclock";
};

And this is also required: https://github.com/zephyrproject-rtos/zephyr/pull/89670

Please try to test with one of our sample in the SDK so we can align easier. 

[ppatel]

Hi Hung,

I added the changes you suggested.

I modified our prj.conf / XXX_defconfig to the following:

# Enable UART driver
CONFIG_SERIAL=y

# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

# Enable GPIO
CONFIG_GPIO=y

# Enable MPU
CONFIG_ARM_MPU=y

# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y

CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_NRF=y

# use grtc as system timer
CONFIG_NRF_GRTC_TIMER=y
CONFIG_NRF_GRTC_START_SYSCOUNTER=y

# Enable LFRC (internal RC oscillator)
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_FREQUENCY=32768

# Disable LFXO (external 32kHz crystal)
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n

# Disable synthesized LFCLK from HFCLK
CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=y
CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON=y

Also modified the Blinky sample to the minimal:

#include <stdio.h>
#include <zephyr/kernel.h>

#define SLEEP_TIME_MS   1000

int main(void)
{
    uint32_t counter = 0;
    while (1) {
        printf("Counter: %u\n", counter++);
        k_msleep(SLEEP_TIME_MS);
    }
    return 0;
}

With the above changes,
For NRF54L15 DevKit I see GRTC (GLOBAL_GRTC_NS)-->CLKCFG(0x00020001)-->CLKSEL-->LFLPRC and can confirm Counter value incrementing on UART.

With the same changes,
For FANSTEL BM15C (NRF54L15) module, I see GRTC (GLOBAL_GRTC_NS)-->CLKCFG(0x00000001)-->CLKSEL-->LFXO.
I get stuck with this call stack:

nrfy_grtc_sys_counter_start(NRF_GRTC_Type * p_reg, _Bool busy_wait) (PATH\modules\hal\nordic\nrfx\haly\nrfy_grtc.h:987)
nrfx_grtc_syscounter_start(_Bool busy_wait, uint8_t * p_main_cc_channel) (PATH\modules\hal\nordic\nrfx\drivers\src\nrfx_grtc.c:566)
sys_clock_driver_init() (PATH\zephyr\drivers\timer\nrf_grtc_timer.c:483)
z_sys_init_run_level(enum init_level level) (PATH\zephyr\kernel\init.c:377)
z_cstart() (PATH\zephyr\kernel\init.c:801)
z_prep_c() (PATH\zephyr\arch\arm\core\cortex_m\prep_c.c:220)
z_arm_reset() (PATH\zephyr\arch\arm\core\cortex_m\reset.S:207)

Can you please suggest if I need additional changes to make this work on FANSTEL BM15C module ?

Thanks!