UARTE hardware timeout

Board: nRF5340-DK
SDK: nrf ncs v3.0.2

Hi,

On the project I am working on there is a tight timing constraint for DMA timeout (30-40us).
Also there was a need for specific baudrate.

Regarding baudrate I've successfully added support for it NRF_UARTE_BAUDRATE_307200 and it works as expected.
But, timeout in uart_rx_enable(dev, buf, len, timeout) is not working as expected.
I've did some tests and decreased RX_TIMEOUT_DIV and tested with different timeouts. Basically, timeouts with higher values are working properly (3000us, 300us), but when I come close to ~60us it stops having periodicity

Good case with 300us and divider = 2 - timeout happens every 150us (yellow spikes)


Bad case 80us, divider = 2 (yellows spikes are from rx_timeout handler, not periodic at all)



This are configurations used
CONFIG_UART_ASYNC_API=y
CONFIG_UART_INTERRUPT_DRIVEN=n
CONFIG_UART_2_ASYNC=y
CONFIG_UART_2_INTERRUPT_DRIVEN=n
CONFIG_NRFX_UARTE2=y
CONFIG_SERIAL=y

I've also tried:
CONFIG_UART_2_NRF_HW_ASYNC=y
CONFIG_UART_2_NRF_HW_ASYNC_TIMER=2
CONFIG_NRFX_TIMER2=y
CONFIG_UART_NRFX=y

From what I understood uart_nrfx_uarte.c driver uses only k_timer (software timer) for this timeout, and that is just not precise enough for project use case.

Is there any other configuration I can try, what would be my other options?
Setup a custom "driver" that uses PPI that connects HW timer with UART Rx?
Or, interrupt based UART handler? What would be a impact on CPU with a busy HDLC based protocol?

Thank you in advance

Parents
  • Hi Nemanja, 

    Do you use 32kHz RC as the source for the LFCLK ? Have you used the 32kHz crystal as the clock source ? 

    I think you are coming close to the limit of the driver. The smallest time the LFCLK can count is 30.517us (with some tolerance). 
    You are doing 80us timeout with divider = 2. The CPU has to go through some instructions between the interrupt and the time count. So I'm not so sure 80 with divider = 2 is still in the limit.  
    You may have to modify the driver to be able to achieve smaller timeout. 

    Could you give us a more detailed requirement / how your protocol work so we can give you some advice ?

Reply
  • Hi Nemanja, 

    Do you use 32kHz RC as the source for the LFCLK ? Have you used the 32kHz crystal as the clock source ? 

    I think you are coming close to the limit of the driver. The smallest time the LFCLK can count is 30.517us (with some tolerance). 
    You are doing 80us timeout with divider = 2. The CPU has to go through some instructions between the interrupt and the time count. So I'm not so sure 80 with divider = 2 is still in the limit.  
    You may have to modify the driver to be able to achieve smaller timeout. 

    Could you give us a more detailed requirement / how your protocol work so we can give you some advice ?

Children
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