Issue with uploading code to custom board

[Raschke]

Hello, 

I am attempting to program to a custom board using VS Code. I am using the Bluetooth beacon advertising example from BLE fundamentals Lesson 2 Exercise 1.

I am getting an error when attempting to access the memory of my device.

I've uploaded a picture of the printed error.

I've also tried using the quick start app to upload the hello world example in the NRF desktop and am having the same issue. I've uploaded the associated logfile.

Are there any areas you'd reccomend looking into?

I've gone over the board and all connections seem to be stable.

Fullscreen 2025-09-02T00_14_28.037Z-log.txt Download

2025-09-02T00:14:28.615Z INFO Initialising the bundled nrfutil device
2025-09-02T00:14:28.647Z DEBUG Started watching devices
2025-09-02T00:14:32.202Z INFO Using the bundled core version for nrfutil device: 8.1.1
2025-09-02T00:14:32.418Z INFO Using nrfutil-device version: 2.10.2
2025-09-02T00:14:32.418Z INFO Using nrf-device-lib version: 0.17.71
2025-09-02T00:14:32.419Z INFO Using nrf-probe version: 0.38.0
2025-09-02T00:14:32.419Z INFO Using JLink version: JLink_V8.22
2025-09-02T00:14:32.420Z INFO Your version of SEGGER J-Link (8.22) is newer than the one this app was tested with (8.18). The tested version is not required, and your J-Link version will most likely work fine. If you get issues related to J-Link with your devices, use the tested version.
2025-09-02T00:14:34.025Z DEBUG Selected device: nRF52 DK
2025-09-02T00:14:34.086Z DEBUG Changed step: Info
2025-09-02T00:14:42.696Z DEBUG Changed step: Rename
2025-09-02T00:14:45.062Z DEBUG Changed step: Program
2025-09-02T00:16:04.301Z DEBUG Changed step: Verify
2025-09-02T00:16:07.311Z INFO Opened port with options: {"path":"COM14","baudRate":115200}
2025-09-02T00:16:08.415Z ERROR Failed with exit code 1.
One or more reset tasks failed:
 * 1050325190: Device error: Failed to write DebugPort register 0x08: Unknown Error in J-Link DLL (error code =-1) (Generic).
Message: Failed to reset 1050325190, Device error: Failed to write DebugPort register 0x08: Unknown Error in J-Link DLL (error code =-1).
2025-09-02T00:16:08.430Z INFO Closed port: COM14
2025-09-02T00:16:11.424Z DEBUG Changed step: Program

[JONATHAN LL]

HI,

How have you connected to the custom board? 


Is the voltage the same on both the the custom board and the debugger board? (are you using a DK as the programmer?)




On our newer DK's that has the nRF5340 as the debug controller this is the way to interface with the custom board. If you are using the pin header P19 then you might still need to tie the VDD to the same voltage as well.

Regards,
Jonathan

[Raschke]

Hi Jonathan,

I have connected to the custom board with the connections shown above. 
I am using the DK as the programmer.

It seems to be connecting to the board but unable to access memory.

[JONATHAN LL]

Raschke said:

The custom board was ordered and soldered by JLCPCB so it was not hand soldered. 

JLCPCB can have some issues with the smaller package types and the aQFN packages, soldering these can be a bit tricky and we often see some mistakes here done by JLCPCB for smaler batches. 

The schematic file you uploaded is blank, cant see anything in it. 

From the image it looks like this is a two layer PCB, and the ground is on the bottom layer? does it cover the entire bottom side? 

We do reviews on both schematics and layout and will do our best to help our customers cross the finish line with a good product design here. 

We also have a guide here: https://devzone.nordicsemi.com/guides/hardware-design-test-and-measuring/b/nrf5x/posts/nrf52832-specific-pcb-guidelines 
and: https://devzone.nordicsemi.com/guides/hardware-design-test-and-measuring/b/nrf5x/posts/general-pcb-design-guidelines-for-nrf52-series 

Also looks like it might be only through hole vias, this is not the best for the CSP package variant. 


If you have the GERBER files I can provide some feedback.

Regards,
Jonathan

[Raschke]

Thank you Jonathon,

That's correct. It is a 2 layer PCB with ground on the bottom layer, which covers the entire bottom side.

I would really appreciate a design review.

I've uploaded the GERBER files in the zipped folder. Let me know if there are any issues with this upload.

All the best,

John

Probe_Benchtop_Moved_PTH_Drill.zip

[JONATHAN LL]

Still not able to see the schematic. 


Center pad area here where the ground is, it should also connect to the first decupling cap of the RF matching. 


There is more then enough space here for you to copy the ref layout. 

Also for such a big PCB it would be easier to get a QFN package, and JLCPCB can also successfully make those. The CSP package variant with the ball grid pins has been a issue for us and other customers when ordering from JLCPCB. 

Its verry likely that there is a solder issue here. 

Regards,
Jonathan

[Raschke]

Thanks for the review Jonathon.

I did miss that connection in the design.

This PCB is a benchtop system to test the components with the final product intended to be much smaller. Hence, the testing of a smaller package.

Thank you for the help with this.

Is there another vendor you can recommend other than JLCPCB? Or is this an issue that is likely to occur from most places?

I've uploaded another copy of the schematic. Let me know if this finally works.

6746.Custom_Board_NRF52832.pdf

[JONATHAN LL]

You can try and work together with JLCPCB to work out the issues, they do have good support form my experience, but the BGA package types we have tend to have a higer failure rate at JLC form our experience. 

Schematic looks ok. 

But we dont relay have any go to recommendations for manufacturers, but we recommend that you try to follow up with the ones you pick and ask them if they have experience and if they can provide any guarantees. 

It might be that they are using a stencil that is to thick and end up using to much solder paste. We use about 80um ourselves but a reduction in stencil openings might also solve this issue. 

And sometimes a re-flow also works to fix this issue. 

Regards,
Jonathan