nPM1300 VOUT timing?

Hello,

For a project with nRF9151 as the main microcontroller, we use nPM1300 for power management.

As I understand, for nRF9151, VDD voltage should be supplied prior to VDD_GPIO voltage.

VDD is supplied from VSYS on nPM1300 and VDD_GPIO is supplied from VOUT2 on nPM1300.

How is the timing between VSYS and VOUT2 for nPM1300? Will there be any delay?

BR Per

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  • Hi,

    Regarding VSYS and VOUT2, if battery is connected and PMIC is active then VBAT will be seen on the VSYS. Also VSYS is the supply for buck (VOUT2) so VSYS needs to be present before buck can start. Buck startup time is 1.2ms so this is the time that it takes from enabling buck to get it on pin. You can control the buck through software TWI interface if you want more specific timing and voltage. 
    Here is the diagram from datasheet:





    Best regards,
    Ressa

Reply
  • Hi,

    Regarding VSYS and VOUT2, if battery is connected and PMIC is active then VBAT will be seen on the VSYS. Also VSYS is the supply for buck (VOUT2) so VSYS needs to be present before buck can start. Buck startup time is 1.2ms so this is the time that it takes from enabling buck to get it on pin. You can control the buck through software TWI interface if you want more specific timing and voltage. 
    Here is the diagram from datasheet:





    Best regards,
    Ressa

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