Optimizing for low-noise and power efficiency: Power LDO from buck VOUT or VSYS?

[leon_nowatch]

Hello,

we are building a custom PCB using the nPM1300. We need a low-noise 1V8 rail for a sensitive analog component and are wondering what the best setup for that would be.

We would like to use the nPM1300's LDO do achieve a low noise rail. With the nPM1300 we would have two options:

1) Set one of the BUCKs to 3V3, and use that to power the LDO

2) Power the LDO directly from VSYS

I would assume that option 2) would result in less noise, but it might also mean a higher idle power consumption since the drop from VSYS to 1V8 will be higher than from the fixed 3V3 BUCK rail to 1V8. As such, option 1) might be more power efficient. What do you think and which option would you recommend?

I was also looking to find out what kind of noise and noise rejection the LDOs in the nPM1300 have, but was unable to do find any measurements. Do you have any information there?

[mathiaso]

Hi again, Leon.

I've got some answers for you now.

From a PSRR point of view, powering the LDO from VSYS would be the better option, compared to powering it from the buck output. This is when considering that the buck is in hysteretic mode, where the ripple is higher when compared to PWM mode.

Typical PSRR values in continuous reference mode (this means one of the bucks is in PWM, or charging is enabled):
 

In sampled mode (bucks in ULP mode and VBUS is disconnected), the LDO reference is sampled with a certain cadence to reduce current consumption. In this mode, the LDO output has some periodic ripple, see in the example below what the LDO output would look like with 1.8V output voltage and 10uA load.
 

So, in this mode, the ripple caused by the sampled reference is dominating the PSRR, and thus, it wouldn't make sense to even measure the PSRR in this case.

In short, if lowest noise is the top priority, power the LDO from VSYS.
If efficiency matters more, power the LDO from the 3.3V buck.

Best regards,
Mathias