SPIS on nRF54L15 doesn't work, get stucked waiting event from EasyDMA

[Pier]

Hi all,

I'm trying to use SPI Slave on a proprietary Hardware that use Ezurio BL54L15 (that contain a Nordic nRF54L15 chip). The environment is VSC + nRF Connect SDK 3.1.1.

 

As a first step I got the example from https://github.com/too1/ncs-spi-master-slave-example using only the slave part (the master is another MCU on our board).

I configured SPIS to use the dedicated pin on Port 2 (clk, MISO, MOSI and another pin for CSN).

What I can see is SPIS driver is waiting for EVENTS_END by Easy DMA that never comes. Looking with a debugger seems that SPIS configuration is ok (PSEL and DMA). If I generate the event with the debugger the SPIS driver respond correctly

CLK and MISO are working, I can see the default char going out with an oscilloscope; CSN seems to be ignored by the SPIS/EasyDMA; MOSI I don't know, never see a rx char coming.

 

So I went using the Development kit Ezurio DVK BL54L15 (that is similar to nRF54L15 DK) to see if could be some trouble with our hardware.

 

This time I used the SPI master slave example as is, without modification.

I only added a nrf54l15dk_nrf54l15_cpuapp.overlay (the 54l15 was not in the example)

&pinctrl {
	spi_master_default: spi_master_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
					<NRF_PSEL(SPIM_MOSI, 0, 0)>,
					<NRF_PSEL(SPIM_MISO, 0, 1)>;
		};
	};

	spi_master_sleep: spi_master_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
					<NRF_PSEL(SPIM_MOSI, 0, 0)>,
					<NRF_PSEL(SPIM_MISO, 0, 1)>;
			low-power-enable;
		};
	};

	spi_slave_default: spi_slave_default {
		group1 {
			psels = <NRF_PSEL(SPIS_SCK, 2, 6)>,
					<NRF_PSEL(SPIS_MOSI, 2, 9)>,
					<NRF_PSEL(SPIS_MISO, 2, 8)>,
					<NRF_PSEL(SPIS_CSN, 2, 10)>;
			// psels = <NRF_PSEL(SPIS_SCK, 2, 1)>,
			// 		<NRF_PSEL(SPIS_MOSI, 2, 4)>,
			// 		<NRF_PSEL(SPIS_MISO, 2, 2)>,
			// 		<NRF_PSEL(SPIS_CSN, 2, 0)>;
		};
	};

	spi_slave_sleep: spi_slave_sleep {
		group1 {
			psels = <NRF_PSEL(SPIS_SCK, 2, 6)>,
					<NRF_PSEL(SPIS_MOSI, 2, 9)>,
					<NRF_PSEL(SPIS_MISO, 2, 8)>,
					<NRF_PSEL(SPIS_CSN, 2, 10)>;
			// psels = <NRF_PSEL(SPIS_SCK, 2, 1)>,
			// 		<NRF_PSEL(SPIS_MOSI, 2, 4)>,
			// 		<NRF_PSEL(SPIS_MISO, 2, 2)>,
			// 		<NRF_PSEL(SPIS_CSN, 2, 0)>;
			low-power-enable;
		};
	};
};

my_spi_master: &spi30 {
	compatible = "nordic,nrf-spim";
	status = "okay";
	pinctrl-0 = <&spi_master_default>;
	pinctrl-1 = <&spi_master_sleep>;
	pinctrl-names = "default", "sleep";
	cs-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
	reg_my_spi_master: spi-dev-a@0 {
		reg = <0>;
	};
	/delete-property/ rx-delay-supported;
	/delete-property/ rx-delay;
};

my_spi_slave: &spi00 {
	compatible = "nordic,nrf-spis";
	status = "okay";
	pinctrl-0 = <&spi_slave_default>;
	pinctrl-1 = <&spi_slave_sleep>;
	pinctrl-names = "default", "sleep";
	def-char = <0x33>;
	/delete-property/ rx-delay-supported;
	/delete-property/ rx-delay;
};

&pwm20 {
	status = "disabled";
};
&uart00 {
	status = "disabled";
};
&uart20 {
	status = "disabled";
};
&uart30 {
	status = "disabled";
};
&nfct {
	status = "disabled";
};
&temp {
	status = "disabled";
};
&adc {
	status = "disabled";
};

 

I tested using SPIS00 (or SPIS20) and pin equal to our board:

 

SCK	Pin 2.01
MOSI	Pin 2.04
MISO	Pin 2.02
CSN	Pin 2.00

 

I got the same behaviour, SPIS is stuck waiting EVENTS_END from Easy DMA

 

Then I tested using SPIS00 (or SPIS21) and pin

 

SCK	Pin 2.06
MOSI	Pin 2.09
MISO	Pin 2.08
CSN	Pin 2.10

 

This works fine, I can receive char from master correctly.

 

SPI RX: 0x00, 0x2d
SPI SLAVE RX: 0x2d, 0x00
SPI SLAVE TX: 0x00, 0x2e
SPI TX: 0x2e, 0x00
[00:00:46.012,517] <dbg> spi_nrfx_spim: spi_context_buffers_setup: tx_bufs 0x20002a20 - rx_bufs 0x20002a10 - 1
[00:00:46.012,530] <dbg> spi_nrfx_spim: spi_context_buffers_setup: current_tx 0x20002a28 (1), current_rx 0x20002a18 (1), tx buf/len 0x2000113c/2, rx buf/len 0x20001138/2
[00:00:46.012,567] <dbg> spi_nrfx_spim: spi_context_update_tx: tx buf/len 0/0
[00:00:46.012,576] <dbg> spi_nrfx_spim: spi_context_update_rx: rx buf/len 0/0
[00:00:46.012,585] <dbg> spi_nrfx_spim: finish_transaction: Transaction finished with status 0
SPI RX: 0x00, 0x2e
SPI SLAVE RX: 0x2e, 0x00
SPI SLAVE TX: 0x00, 0x2f
SPI TX: 0x2f, 0x00
[00:00:47.012,751] <dbg> spi_nrfx_spim: spi_context_buffers_setup: tx_bufs 0x20002a20 - rx_bufs 0x20002a10 - 1
[00:00:47.012,762] <dbg> spi_nrfx_spim: spi_context_buffers_setup: current_tx 0x20002a28 (1), current_rx 0x20002a18 (1), tx buf/len 0x2000113c/2, rx buf/len 0x20001138/2
[00:00:47.012,799] <dbg> spi_nrfx_spim: spi_context_update_tx: tx buf/len 0/0
[00:00:47.012,808] <dbg> spi_nrfx_spim: spi_context_update_rx: rx buf/len 0/0
[00:00:47.012,817] <dbg> spi_nrfx_spim: finish_transaction: Transaction finished with status 0

So the question is, why I can't use pin 00-04 of port 2 but I can use pin 06-10 of the same port? The are some limitation? But in this case why are not documented? I need some extra configuration that I miss? But in example + DK the configuration is the same.

 

Last note:

Also using

CONFIG_SPI_LOG_LEVEL_DBG=y

I can't get any debug message from SPIS library code, but I get from SPIM. Do I need a different flag to configure this?

Thanks,

Pier

[Ressa]

Hi,

Thanks for contacting us. Please note that for different peripherals you have limited pin selection options. You can see the pin assignment page for more details about the restriction on selecting specific pins for different peripherals: Pin assignments

for CSN line you can use either P2.10 or P2.05 , P2.00 is not allowed. 


Best regards,
Ressa

[Pier]

Hi Ressa,

tested using P2.05 on the DVK and it works.

I checked for info about pins on the datasheet, but in v0.8 (version of document the we have) nothing was mentioned about SPIS CS, now in v1.0 (released september 25) is updated. 

The design for hw board is 3 months old, and so, without without specific advise, was used one of the available pin.

Now need to modify the hw to test on the actual board.

Thank you

Pier