Issue After Power Cycle – BLE and Sensor Not Working Properly (nRF SDK Toolchain 3.0.2 / nRF Connect SDK 3.1.0)

Hi,

When the firmware is run in debug mode (J-Link connected), the system always works correctly. BLE initializes properly, and all sensors function as expected.

When the device is powered from the battery and undergoes a full power cycle (complete power cut or battery disconnect/reconnect) without a debugger attached, the system does not function correctly. BLE and/or sensors fail to initialize properly.

Repeating the same power-cycle process with the debugger attached immediately resolves the issue.

This indicates that the problem occurs only during a cold boot in release mode, and the presence of the debugger masks the issue.

From our analysis, this behavior suggests a power-up, reset, clock, or initialization timing issue, rather than a functional issue in the BLE stack or sensor drivers themselves.

Key observations:

BLE and sensors work correctly when tested individually.

The failure occurs only when both are initialized together after a cold power-on.

Debug mode likely introduces additional delays, stabilizes the power rail, or alters reset/clock startup behavior, allowing the system to initialize correctly.

During a cold boot without the debugger, the application may start executing before:

The power rail is fully stable

HFCLK/LFCLK is ready

External sensors have completed their power-up sequence

We suspect this may be related to:

prj.conf configuration (clock control, power management, DC/DC, logging)

Sensor power sequencing or missing startup delays

Reset or brown-out behavior during battery reconnect

Initialization order or timing differences between debug and release builds

We would appreciate your guidance on:

Recommended prj.conf settings for reliable cold-boot behavior

Best practices for clock and power initialization in battery-powered systems

Any known issues in nRF Connect SDK v3.1.0 related to cold boot vs debug behavior

Please let us know if you need additional information, logs, or a reduced test case.

Best regards,
Kinjal Sarda

Parents
  • 1. It could be that your project is set up for using the DCDC while your custom board is designed for LDO mode. If this is the case it is likely that it works in Debug mode because LDO mode then is forced. Try configuring this in your devicetree:

    &vregmain {
        status = "okay";
        regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
    };

    or like this: 

    &reg {
    regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
    };

    2. If 1. does not work, we could look into the clock sources. Are you using an external crystal for the 32.768kHz clock? 

  • Hello,

    Thank you for your guidance and detailed explanation.

    The issue has been resolved based on your reply and recommendations. The system is now working as expected.

    We appreciate your support and prompt assistance.

    Best regards,
    Kinjal Sarda

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