nRF5340 PDM CLK duty cycle

[Poki Huang]

Hi 

1. At nRF5340 datasheet page 420, the PDM duty cycle is 40%~60%, any register can tune duty cycle? Or it's nRF5340 variation tolerance?

2. Since our DMIC IM69D128S duty cycle spec. is 45%~55%, we test 2 pcs PCB and find if we tune frequency, the duty cycle will change(see below pic.), can we use this way to tune duty cycle or not?

Thank you

 

Poki

[Ressa]

Hi Poki,

Duty cycle of clock signal for PDM cannot be controlled and the variation mentioned in "PDM Electrical Specification" is due to internal hardware specs. 

Best regards,
Ressa

[Poki Huang]

Hi Ressa:

What about my question 2? We change the frequency and from 1.28MHz to 960KHz and find the duty cycle from 55.54% to 49.97%, we test two pcbs and the result is the same, so can we use this frequency setting to let the ducy cycle inside our DMIC spec.? Or the duty cycle may change if next time with different lot/date code of nRF5340?

Thank you

Poki

[Ressa]

Hi Poki,

That's a good observation but there is no official document to guarantee that observation for all conditions. But as a general rule you would expect stable signal characteristics for lower frequencies as you observed.