Unable to get nrf54L15 on Fanstel BM15M to wake with GRTC after sys_poweroff

Hi Nordic folks,

I'm trying to get the nrf54L15 in a Fanstel BM15M to go into the system OFF state and be woken up later by a timer.  All the documentation I've seen says there's an internal LRFC that can be used, and that an external crystal is not required.  After a couple of days of attempting many solutions and tests, I have not been able to get it to do so. 

Context

Custom board based on BM15M module (nRF54L15). No external 32.768 kHz crystal. NCS v3.0.2, nRF54L15 (HALTIUM family).

  • CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y → Zephyr GRTC driver selects CLKCFG.CLKSEL=LFLPRC
  • CONFIG_POWEROFF=y, CONFIG_NRF_GRTC_START_SYSCOUNTER=y

What We Tried

Used z_nrf_grtc_wakeup_prepare(N) followed immediately by sys_poweroff(). No Zephyr timer calls between the two — all inter-call delays use k_busy_wait only.

Register State Immediately Before sys_poweroff()

Read back via direct register access (NRF_GRTC->MODE and NRF_GRTC->CLKCFG) and reported via backlight blink codes. Confirmed:

  • MODE.AUTOEN = 0 (SYSCOUNTER always-on ✓)
  • MODE.SYSCOUNTEREN = 1 (SYSCOUNTER running ✓)
  • CLKCFG.CLKSEL = 2 (LFLPRC ✓)

z_nrf_grtc_wakeup_prepare() returned 0 (success). CC compare set to T+15 seconds, with sufficient k_busy_wait latching time after wakeup_prepare.

Observed Behavior

J-Link was disconnected (battery power only → real System OFF, not simulated WFE loop). Device enters System OFF. After 15 seconds: no cold reset. Device remains in System OFF. RESET_CLOCK bit never appears in RESETREAS.

Previous Hypotheses Eliminated

  • CCEN=1 required for wake: Enabled CCEN on all 12 channels before poweroff → no change
  • J-Link causing simulated System OFF: Disconnected J-Link and repeated → still no wake
  • AUTOEN not 0: Register readback confirmed AUTOEN=0
  • CLKSEL wrong: Register readback confirmed CLKSEL=LFLPRC=2

Root Cause Hypothesis

LFLPRC does not actually run in System OFF on nRF54L15, despite:

  • nrf_grtc_timer.c explicitly setting CLKCFG.CLKSEL=LFLPRC when K32SRC_RC=y
  • LFLPRC being described as a low-power oscillator intended for System OFF

Supporting evidence: The Nordic system_off sample targets nRF54L15dk (nrf54l15dk/nrf54l15/cpuapp). A prior build of that sample on this machine shows CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y — the nRF54L15 DK uses an external LFXO crystal, not LFLPRC. The sample GRTC wake test is only validated on boards with a crystal.

Questions for Nordic

  1. Does LFLPRC actually keep running during nRF54L15 System OFF? Can GRTC generate a System OFF wake event when CLKCFG.CLKSEL=LFLPRC?

  2. Is there an additional initialization step required to keep LFLPRC alive across System OFF — e.g., a specific NRFS request, SYSCTRL domain retention register, or GRTC active_request that must be made before sys_poweroff()?

  3. Is NRF_GRTC_CLKSEL_LFLPRC (value 2) intended to work for System OFF wake, or only for WFI sleep? The Zephyr nrf_grtc_timer.c driver sets this when K32SRC_RC=y, and z_nrf_grtc_wakeup_prepare() relies on it — if LFLPRC doesn't run in System OFF, this API silently does nothing on no-crystal boards.

  4. The Nordic DevZone references LFXO as the only System OFF GRTC clock source (devzone.nordicsemi.com/f/nordic-q-a/117845/grtc-feature-of-nrf54l15). Is this correct for nRF54L15, or is LFLPRC a valid alternative?

Build Configuration (Relevant Kconfig)

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_FORCE_ALT=y
CONFIG_NRF_GRTC_START_SYSCOUNTER=y
CONFIG_NRF_GRTC_TIMER_AUTO_KEEP_ALIVE=y
CONFIG_NRF_GRTC_TIMER_CLOCK_MANAGEMENT=y
CONFIG_POWEROFF=y

Next Steps (Pending Nordic Clarification)

  • If LFLPRC cannot be used: add LFXO (XL1/XL2 pins) on V7 board revision
  • If initialization step is missing: apply fix and re-test
  • Current workaround: k_sleep() (WFI) for timer-based CTP polling (~987µA vs ~184µA System OFF)

All the documentation I've read said an external crystal is not required, and so I'm trying to nail this down before I do another PCB revision. 

Thanks,

Steve

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