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  • Case ID: 358934
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clarification about GRTC.SYSCOUNTER when in low-power sleep

bios-bob

i have a trivially simple "bare-metal" (register-level) test case in which i setup GRTC as follows:

MODE.SYSCOUNTEREN = 1
TASKS.START = 1
TIMEOUT = 2

i also have the LFXTAL configured as my LFCLK....

after this, i go into an *indefinite* sleep....  no GRTC wakeups have been scheduled....

all other things being equal, i find that this (benign) setup adds 0.4uA of *extra* current consumption when sleeping....  (2.1uA without, 2.5uA with)....

i've verified that no SYSCOUNTER[i] is ACTIVE.... 

i've "discussed" this with your AI (very helpful!!!), but it ultimately said we need to ask a human to clarify....  ;-)

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  • 0

    Hi,

     

    If you write to any of the registers mentioned here, it will be active in sleep mode:

    https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/grtc.html#d763e406

     

    all other things being equal, i find that this (benign) setup adds 0.4uA of *extra* current consumption when sleeping....  (2.1uA without, 2.5uA with)....

    Which mode(s) are you testing?

    The expected SystemOnIdle current, with full RAM retention, with- and without GRTC, is specified to be just below 3 uA (2.7 vs 2.9):

    https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/chapters/current_consumption/doc/current_consumption.html#ariaid-title4

     

    Kind regards,

    Håkon 

  • 0 in reply to Håkon Alseth

    i'm not touching any of the GRTC registers which would make SYSCOUNTER active....  i've also verified that the ACTIVE bit is indeed 0....

    what i recently discovered was that i was *not* setting up the CLKCFG register -- which by default is set to LFCLKSRC....  now i have setup the LFCLK to use the LFXTAL -- but apparently i should also explicitly set CLKCFG to LFXTAL as well....

    while everything "works", i found that explicitly setting CLKCFG saved about 0.2uA when sleeping.... my test case is *only* retaining a single 16K SRAM block, which puts me closer to the 2.2uA range....

    i'm trying to match the sleep current achived in nordic's submission to the BlueJoule benchmark (2uA), found at https://github.com/em-foundation/BlueJoule/blob/main/captures/nrf-54-dk/zephyr2-3V0-J/ABOUT.md

    i (wrongly) presumed that the default setting for CLKCFG would be sufficient -- especially since i already bound LFXTAL as my LFCLK....  for whatever reason, it introduced about 0.2uA of additional sleep current....

    i'm still not quite in parity with nordic's code; another 0.2uA to go....  

  • 0 in reply to bios-bob

    Hi,

     

    I setup a test project in zephyr (first 4 blocks on, system on idle):

    system_on_idle_test_nrf54l15.zip

    Where I tried to replicate the setup that you have. Sorry for the magic numbers on the register level.

    Testing on nRF54L15-DK, with "almost everything" disabled in the board controller application, and 3.0V:

     

    I measure a difference of approx. 0.2 uA if I start the LFXO + setup the GRTC as you initially mention.

    No LFXO: 1.6 uA

    LXFO + RTC: 1.77 uA

     

    As there is a write to the registers mentioned in the docs, the LFXO/GRTC will be kept on, accounting for the added ~0.2 uA:

      

    If you are unsure of the difference between the SoftDevice setup vs. the bare-metal approach, and you think it is related to the clock configuration, you could use Segger Ozone to enter debug mode and look at the register content in both projects, to see if there is anything directly different between the two setups.

     

    Kind regards,

    Håkon

  • 0 in reply to Håkon Alseth

    i can confirm that there is a 0.2uA difference when i tested your project on my end....  my measurements  were 2.5uA (without GRTC) and 2.7uA (with GRTC) at 3V....  (i must have "old" silicon on my DK???)

    i'm attaching the program Pal Haland submitted....  when idle, it only saves one 16K block of SRAM....  otherwise, i believe all peripherals are disabled when sleeping -- except for the GRTC....

    1373.beacon_advertiser.zip

  • 0 in reply to bios-bob

    Hi,

     

    Thank you for attaching the test fw. I am measuring 1.2 uA "between the events" on this firmware:

    I locked the scale here, to show where the ULP (ultra low power) regulator starts "taking over". Measurements before this period is relying on stored energy on the external caps from the previous active power mode, so will be lower than 1.2 uA until it switches fully over to ULP mode.

     

    Setting the same retention configuration in NRF_MEMCONF as my former example gives the same, ie. 1.7 uA, as I previously measured.

    bios-bob said:

    (i must have "old" silicon on my DK???)

    It does indeed sound like there is something leaking on the DK that you have. It should be half of what you measure.

    I have tested on nRF54L15-DK "PCA10156 v1.0.0" on my side. What does yours state?

     

    Have you turned off features in nRF connect for desktop -> "Board configurator" application? These features, uart/external flash etc, can potentially leak smaller currents when enabled, which _could_ be the reason for the added around 1 uA floor that you're seeing.

     

    Kind regards,

    Håkon

  • 0 in reply to Håkon Alseth

    i'm at v0.9.2 -- but do have another board coming tomorrow....  we'll pick this up then....

  • 0 in reply to bios-bob

    That sounds good. Let me know how it goes!

     

    Kind regards,

    Håkon

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