Regarding the SPI specifications of the nrF52840

[Kanda]

This question concerns the description of the SPI communication Electrical Specifications on page 425 of the nRF52840 Product Specification.

The values ​​for "t_spim_vmo" is stated as 59ns for frequencies below 8MHz and 8ns for frequencies above 8MHz.

If the clock is 8MHz, the time between the falling and rising edges is 62.5ns.
However, a "t_spim_vmo" of 59ns seems too large.

Do the values ​​of 59ns and 8ns switch automatically when the clock frequency is selected?
Or Is it possible to switch it using a register somewhere?

Are there any measurement conditions for the 59ns specification? For example, a wiring capacitance of 100pF?

If the clock is 8MHz and the time between the falling and rising edges is 62.5ns, considering the "t_su (setup time)" of the SPI communication partner circuit,
Since "t_spim_vmo" has a maximum response time of 59ns, there is a possibility that data output may not be completed in time.
Is it okay to use it with an 8MHz clock? And what are the reasons why is it okay?

[Hung Bui]

Hi Takeshi, 
I have some initial answer from the team. What you see in the table below of t_SPIM,VMO,HS = 8ns, comes from the SPIM HS peripheral specification (SPIM3)

The information we got from the team is that 8ns applied for also clock <=8MHz if you use SPIM HS. So in your case it's a good choice to move to SPIM3 (High Speed)

Another option is to use nRF54L , t_SPIM_VMO is only 28ns on nRF54L. 

[Kanda]

Hi Hung

Thank you for your reply.

I now understand that using SPIM3, the response will be 8ns even at clock frequencies <= 8MHz.

Thank you for your cooperation.

Best regards,

Takeshi Kanda