Regarding the SPI specifications of the nrF52840

[Kanda]

This question concerns the description of the SPI communication Electrical Specifications on page 425 of the nRF52840 Product Specification.

The values ​​for "t_spim_vmo" is stated as 59ns for frequencies below 8MHz and 8ns for frequencies above 8MHz.

If the clock is 8MHz, the time between the falling and rising edges is 62.5ns.
However, a "t_spim_vmo" of 59ns seems too large.

Do the values ​​of 59ns and 8ns switch automatically when the clock frequency is selected?
Or Is it possible to switch it using a register somewhere?

Are there any measurement conditions for the 59ns specification? For example, a wiring capacitance of 100pF?

If the clock is 8MHz and the time between the falling and rising edges is 62.5ns, considering the "t_su (setup time)" of the SPI communication partner circuit,
Since "t_spim_vmo" has a maximum response time of 59ns, there is a possibility that data output may not be completed in time.
Is it okay to use it with an 8MHz clock? And what are the reasons why is it okay?

[Hung Bui]

Hi Takeshi, 

Could you please explain a bit more on your concern when you mentioned about "59ns seems too large". This maximum number gives a small buffer to the edge to edge time at 62.5ns as you mentioned. 
Please be noted that this is the MAX value, so it's the worst case scenario. 
Are you thinking of external parasitic capacitance that can cause the t_spim_vmo to drag a little bit more. 
My understanding is that the measurement should be done similar to what described at note 33 in the page above. 

 

My understanding is that the peer device, for example in CPOL=0, CPHA=0, should only start sampling at the raising edge of the clock. The MOSI should be valid 3.5 ns before the sampling happen  . So I don't fully get why you worry about t_su ? If there is a t_su then it add more buffer to the sampling and you will be on the safe side that the value of MOSI should be valid by the time of sampling. 

[Kanda]

Hi Hung

Thank you for your reply.
For example, "t_su" of slave is 15ns.
The voltage needs to valid 15ns before the rising edge.
If the clock is 8MHz, the time between the falling and rising edges is 62.5ns.
　　　　　 62.5ns - 15ns = 47.5ns
The output needs to valid within 47.5ns.
However, the nRF52840's "t_spim_vmo" time is 59ns.
Therefore, I thought "t_spim_vmo" was too large.

[Hung Bui]

Hi Takeshi, 
You are right. t_su actually requires the MOSI line to be stable before the clock edge. Could you provide the product code of the slave you are using so I can check with the team ? 

[Kanda]

The product code of the slave is ADXL382-1.
Thank you for your cooperation.

[Hung Bui]

Hi Takeshi, 
I have some initial answer from the team. What you see in the table below of t_SPIM,VMO,HS = 8ns, comes from the SPIM HS peripheral specification (SPIM3)

The information we got from the team is that 8ns applied for also clock <=8MHz if you use SPIM HS. So in your case it's a good choice to move to SPIM3 (High Speed)

Another option is to use nRF54L , t_SPIM_VMO is only 28ns on nRF54L.