case about nRF54L15-QFAA reset pin

[peter.min]

Hi,

1.The customer does not require an external hardware reset circuit. How should the reset pin be handled externally?

2. Can R1 and C13 be omitted?

3. If R1 cannot be omitted? So, should R1 be left dangling?

Best regards,

Peter.Min

[Ressa]

Hi Peter,

The components on reset pin (R1 and C13) are not for reset pin functionality, it is about suppressing potential harmonics radiations from rest pin. It is about regulatory certificates. So the official recommendation is to keep them and R1 should be connected to VDD of SoC if you are not using it. R1 should not be left floating if you want to keep it (leaving it float does not cause problem but goes against the purpose of having it). Also please note that reset pin already has a permanent pull up resistor. 

Best regards,
Ressa

[peter.min]

Hi Ressa,

1. What are the benefits of connecting R1 to VDD, and what are the effects on power consumption?
2. What are the consequences of not soldering R1, and what is the resistance value of the internal pull-up on RESET?
3. What is your suggestion for the customer regarding how to design this reset circuit?

Best regards,

Peter.Min

[Ressa]

Hi Peter,

1. Those R and C are supposed to act like a low pass filter. The filter components need to be connected to AC ground to perform their job. For R if you are not using it, you need to either connect it to GND or VDD. If you connect it to ground it will cause current leakage through internal pull up resistor and you do not want it. Also the voltage level on the reset pin will be somewhere between GND and VDD which we do not want it. Only correct option is to connect it to VDD. It will not cause current leakage and no issue with voltage level on reset pin. It will act like second pull up.

2. Just having the cap also acts like a low pass filter or more precisely like a notch filter that can dampen the potential leaked harmonics through reset pin. In that case R can be removed. R is to make the filter slightly wider to cover more frequency range. Internal pull up on rest pin can be found in below table:

GPIO Electrical Specification • nRF54L15 | nRF54L10 | nRF54L05 Datasheet • Technical Documentation


3.

peter.min said:

3. What is your suggestion for the customer regarding how to design this reset circuit?

As mentioned before, best practice is to keep both R and C while R connected to VDD (if reset pin is not used). If you have constraint on number of components, you can remove R and just keep C (C connected to ground as in schematic).