Struggling to isolate custom nRF52840 board from DK on-board debugger

[lassey0]

Hi,

I am developing a custom PCB based on the nRF52840 and am currently trying to flash/debug it using an nRF52840-DK (PCA10056) as an external debugger. 

connected devices like this without the custom board: 

So how do I connect the custom board when I have made testpads for vdd, gnd, swdio, swdclk. No testpad for nReset and no way to get to it anymore.

im seeing in the pca10056 3.0.3 p20 where are connections to 

pin 1: VDD_nRF

pin 2: VDD_nRF

pin 3: SWD SEL

pin 4: SWD IO

pin 5: SWD CLK

pin 6: SWO

pin 7: RESET

pin 8: empty

pin 9: VIN 3-5V

pin 10: VDD nRF_HV

pin 11: VDD nRF_HV

pin 12: VIO REF

pin 13: empty

And which way the all switches needs to be?

[Turbo J]

There are pretty images in the manual how to connect to external targets. Google may not find them currently due to website restructure but they should not be too difficult to locate (hence why I don't provide link here either).

Missing RESET is a redesign.

Any minor mistake in clock/dcdc/bootloader config likely requires a recovery operation - that is timed to RESET.

[lassey0]

Sidenote: 

We performed direct CTRL-AP register reads via J-Link Commander (CTRL-AP.png): 

SWDWriteDP 2 0x01000000 

SWDReadAP 0x00 = 0x00000000  (RESET) 

SWDReadAP 0x04 = 0x00000000  (ERASEALL) 

SWDReadAP 0x08 = 0x00000000  (ERASEALLSTATUS) 

SWDReadAP 0x0C = 0x00000000  (APPROTECTSTATUS) 

All CTRL-AP registers return 0x00000000. This means the chip acknowledges the SWD connection at DP level (DPIDR = 0x2BA01477) and J-Link detects CTRL-AP, but all AP-level register reads return zero. Is this nRF52840 v2 APPROTECT behavior where the chip is locked and blocks all AP access including CTRL-AP register reads and recovery requires a mandatory hardware reset via nRESET pin which is not accessible on this PCB design so pcb is bricked