Struggling to isolate custom nRF52840 board from DK on-board debugger

[lassey0]

Hi,

I am developing a custom PCB based on the nRF52840 and am currently trying to flash/debug it using an nRF52840-DK (PCA10056) as an external debugger. 

connected devices like this without the custom board: 

So how do I connect the custom board when I have made testpads for vdd, gnd, swdio, swdclk. No testpad for nReset and no way to get to it anymore.

im seeing in the pca10056 3.0.3 p20 where are connections to 

pin 1: VDD_nRF

pin 2: VDD_nRF

pin 3: SWD SEL

pin 4: SWD IO

pin 5: SWD CLK

pin 6: SWO

pin 7: RESET

pin 8: empty

pin 9: VIN 3-5V

pin 10: VDD nRF_HV

pin 11: VDD nRF_HV

pin 12: VIO REF

pin 13: empty

And which way the all switches needs to be?

[Simonr]

Hi

How have you confirmed the revision of your board? I don't see anything obvious to do from a schematic level that will enable you to do a reset on your boards.

Best regards,

Simon

[lassey0]

Hi, 

In the chip it says N52840 and QIAAD0 below. Can you confirm that the schema is alright and it should work without the reset pin access

[Simon D-M]

Hi,

Sorry, Simon is not available for the moment, so I'm taking over this case. If you feel like I am missing some context, please feel free to give me the context that I missed.

lassey0 said:

Can you confirm that the schema is alright and it should work without the reset pin access

I'm not a hardware engineer, but it looks OK to me.

Have you tried to use another GPIO pin as a substitute reset pin like Simon proposed in one of his previous message?

Or is it that you can't program your chip at all ?

Best regards,

Simon D-M

[lassey0]

Hi Simon,

Thanks for taking over the case.

Unfortunately, I cannot use another GPIO as a reset pin because this PCB revision is already manufactured. The nRESET pin (P0.18) is not routed anywhere, and since this is the QFN73 package, there is no practical way to probe or wire directly to the pad under the package.

Regarding programming:

• The chip has never been successfully programmed.
• SWD communication is present. J-Link consistently detects the SW-DP (ID 0x2BA01477) and the CTRL-AP.
• However, the AHB-AP/core is never accessible. J-Link reports “Could not find core in Coresight setup,” and both nrfutil device recover and nrfjprog --recover fail because the access port remains protected after erase and reset.
• I have tested with both an nRF52840-DK (PCA10056) and an nRF51-DK (PCA10040) as external debuggers, with identical results.

The marking on the IC is:

N52840

QIAAD0

Could you confirm whether QIAAD0 corresponds to Revision 2 or Revision 3 silicon?

Also, based on the schematic and these symptoms, do you see anything that could explain why the device appears protected before it has ever been programmed? Or does this behavior suggest a hardware issue with the board or the MCU itself rather than the missing nRESET connection?

And can you confirm if these gnd connections are critical errors that are keeping the access to the chip impossible (photo):

 

For example DEC5, P0.30, P0.10 exc.

Thank you for your help.

[Simon D-M]

Hi,

lassey0 said:

The marking on the IC is:

N52840

QIAAD0

Could you confirm whether QIAAD0 corresponds to Revision 2 or Revision 3 silicon?

This is Revision 2. You can see it in the compatibility matrix documentation (link).

lassey0 said:

Also, based on the schematic and these symptoms, do you see anything that could explain why the device appears protected before it has ever been programmed? Or does this behavior suggest a hardware issue with the board or the MCU itself rather than the missing nRESET connection?

I am not too sure about what is happening here... After further checking of the hardware, I can indeed see some issues with the schematic. I am not sure if they are the root of your problem, but they definitely need to be fixed.

The main errors that I could see are:

• DEC4 <---> DEC6: They should be connected together (link).
• DEC5:  currently connected to GND, but should be left floating (link).
• (minor) Leave the unused GPIO pin floating, and it is a good practice to still expose them if you have the space on your PCB.

But please remember that I am not a hardware engineer, so please take it with a grain of salt.

Also, have you made some voltage measurements on your board? Can you please check if the power supply is managing to output a stable voltage?

And are the decoupling capacitors close enough to the nRF52840?

Best regards,

Simon