Hello Nordic team,
We are reviewing our nRF54LM20-CAAA (CSP61) hardware design and would appreciate your clarification on several power and RF related points.
DECRFrelated network
In the reference design,L5 = 1.0 nHis placed betweenDECRFandDECA, andC8 = 1.0 pFis connected across the two nodes.
Could you please clarify:- What are the specific purposes of the
1.0 nHinductor and the1.0 pFcapacitor? - For the
CSP61/CAAAvariant, are these mandatory fixed values, or are they intended as layout/board-dependent tuning components? - If tuning is allowed, what should be optimized when adjusting them: RF performance, supply noise isolation, regulator stability, or something else?
- What are the specific purposes of the
C7marked asNC/DNPin the reference design
In the same network,C7is currently marked asNC/DNP.
Could you please clarify:- What is the intended purpose of reserving
C7? - Under what conditions should
C7be populated? - If it should be populated, what value range or selection criteria do you recommend?
- What is the intended purpose of reserving
- Power-up / power-down timing of
VDD,VBUS, andnRESET
Could you please provide or confirm:- The power-up and power-down timing diagram for
VDD,VBUS, andnRESET; - Any mandatory sequencing constraints, minimum delay requirements, or ordering requirements;
- Any special considerations when
VBUSis present beforeVDD, or whenVBUScomes up afterVDD.
- The power-up and power-down timing diagram for
- Main DC/DC related to
DCC/DECD
For the main DC/DC regulator associated withDCC/DECD, could you please clarify:- What is the actual peak current? If possible, we would like to know both the peak inductor current and the peak load current.
- What is the typical switching frequency?
- Is the
4.7 uHinductor in the reference design mandatory, or can it be adjusted? - If it can be adjusted, what is the supported inductance range, and what are the key selection criteria such as saturation current, DCR, ripple, efficiency, and transient performance?
Thank you.